diff options
author | Karl Kurbjun <kkurbjun@gmail.com> | 2011-02-08 05:53:30 +0000 |
---|---|---|
committer | Karl Kurbjun <kkurbjun@gmail.com> | 2011-02-08 05:53:30 +0000 |
commit | 4d129044390a087b6193b6ce63e035b2550b3ce4 (patch) | |
tree | 88a0400687fd16e2d31378bf69f9435b7fde7ac1 | |
parent | a014191e5e56f153f9ffb63cc953896930712eca (diff) | |
download | rockbox-4d129044390a087b6193b6ce63e035b2550b3ce4.tar.gz rockbox-4d129044390a087b6193b6ce63e035b2550b3ce4.zip |
M:Robe 500: Use bit modifiers more.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29247 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/target/arm/tms320dm320/dsp-dm320.c | 8 | ||||
-rw-r--r-- | firmware/target/arm/tms320dm320/kernel-dm320.c | 4 | ||||
-rw-r--r-- | firmware/target/arm/tms320dm320/timer-dm320.c | 17 | ||||
-rw-r--r-- | firmware/target/arm/tms320dm320/uart-dm320.c | 19 |
4 files changed, 28 insertions, 20 deletions
diff --git a/firmware/target/arm/tms320dm320/dsp-dm320.c b/firmware/target/arm/tms320dm320/dsp-dm320.c index 5f0c997bd2..be9f8d8bd9 100644 --- a/firmware/target/arm/tms320dm320/dsp-dm320.c +++ b/firmware/target/arm/tms320dm320/dsp-dm320.c | |||
@@ -64,10 +64,10 @@ void dsp_reset(void) | |||
64 | { | 64 | { |
65 | DSP_(0x7fff) = 0xdead; | 65 | DSP_(0x7fff) = 0xdead; |
66 | 66 | ||
67 | IO_DSPC_HPIB_CONTROL &= ~(1 << 8); | 67 | bitclr16(&IO_DSPC_HPIB_CONTROL, 1 << 8); |
68 | /* HPIB bus cycles will lock up the ARM in here. Don't touch DSP RAM. */ | 68 | /* HPIB bus cycles will lock up the ARM in here. Don't touch DSP RAM. */ |
69 | nop; nop; | 69 | nop; nop; |
70 | IO_DSPC_HPIB_CONTROL |= 1 << 8; | 70 | bitset16(&IO_DSPC_HPIB_CONTROL, 1 << 8); |
71 | 71 | ||
72 | /* TODO: Timeout. */ | 72 | /* TODO: Timeout. */ |
73 | while (DSP_(0x7fff) != 0); | 73 | while (DSP_(0x7fff) != 0); |
@@ -81,9 +81,9 @@ void dsp_wake(void) | |||
81 | 81 | ||
82 | /* The first time you INT0 the DSP, the ROM loader will branch to your RST | 82 | /* The first time you INT0 the DSP, the ROM loader will branch to your RST |
83 | handler. Subsequent times, your INT0 handler will get executed. */ | 83 | handler. Subsequent times, your INT0 handler will get executed. */ |
84 | IO_DSPC_HPIB_CONTROL &= ~(1 << 7); | 84 | bitclr16(&IO_DSPC_HPIB_CONTROL, 1 << 7); |
85 | nop; nop; | 85 | nop; nop; |
86 | IO_DSPC_HPIB_CONTROL |= 1 << 7; | 86 | bitset16(&IO_DSPC_HPIB_CONTROL, 1 << 7); |
87 | 87 | ||
88 | restore_irq(old_level); | 88 | restore_irq(old_level); |
89 | } | 89 | } |
diff --git a/firmware/target/arm/tms320dm320/kernel-dm320.c b/firmware/target/arm/tms320dm320/kernel-dm320.c index 7c3805eb0e..08c50432e4 100644 --- a/firmware/target/arm/tms320dm320/kernel-dm320.c +++ b/firmware/target/arm/tms320dm320/kernel-dm320.c | |||
@@ -27,7 +27,7 @@ | |||
27 | 27 | ||
28 | void tick_start(unsigned int interval_in_ms) | 28 | void tick_start(unsigned int interval_in_ms) |
29 | { | 29 | { |
30 | IO_CLK_MOD2 |= CLK_MOD2_TMR1; /* enable TIMER1 clock */ | 30 | bitset16(&IO_CLK_MOD2, CLK_MOD2_TMR1); /* enable TIMER1 clock */ |
31 | IO_TIMER1_TMMD = CONFIG_TIMER1_TMMD_STOP; | 31 | IO_TIMER1_TMMD = CONFIG_TIMER1_TMMD_STOP; |
32 | 32 | ||
33 | /* Setup the Prescalar (Divide by 10) | 33 | /* Setup the Prescalar (Divide by 10) |
@@ -42,7 +42,7 @@ void tick_start(unsigned int interval_in_ms) | |||
42 | IO_TIMER1_TMMD = CONFIG_TIMER1_TMMD_FREE_RUN; | 42 | IO_TIMER1_TMMD = CONFIG_TIMER1_TMMD_FREE_RUN; |
43 | 43 | ||
44 | /* Enable the interrupt */ | 44 | /* Enable the interrupt */ |
45 | IO_INTC_EINT0 |= INTR_EINT0_TMR1; | 45 | bitset16(&IO_INTC_EINT0, INTR_EINT0_TMR1); |
46 | } | 46 | } |
47 | 47 | ||
48 | void TIMER1(void) __attribute__ ((section(".icode"))); | 48 | void TIMER1(void) __attribute__ ((section(".icode"))); |
diff --git a/firmware/target/arm/tms320dm320/timer-dm320.c b/firmware/target/arm/tms320dm320/timer-dm320.c index 030d645664..0b7ad893d3 100644 --- a/firmware/target/arm/tms320dm320/timer-dm320.c +++ b/firmware/target/arm/tms320dm320/timer-dm320.c | |||
@@ -45,7 +45,7 @@ bool timer_set(long cycles, bool start) | |||
45 | 45 | ||
46 | oldlevel = set_irq_level(HIGHEST_IRQ_LEVEL); | 46 | oldlevel = set_irq_level(HIGHEST_IRQ_LEVEL); |
47 | 47 | ||
48 | IO_CLK_MOD2 |= CLK_MOD2_TMR0; //enable TIMER0 clock!!!!!!!!! | 48 | bitset16(&IO_CLK_MOD2, CLK_MOD2_TMR0); /* enable TIMER0 clock */ |
49 | 49 | ||
50 | IO_TIMER0_TMMD = CONFIG_TIMER0_TMMD_STOP; | 50 | IO_TIMER0_TMMD = CONFIG_TIMER0_TMMD_STOP; |
51 | 51 | ||
@@ -74,13 +74,16 @@ bool timer_set(long cycles, bool start) | |||
74 | 74 | ||
75 | static void stop_timer(void) | 75 | static void stop_timer(void) |
76 | { | 76 | { |
77 | IO_INTC_EINT0 &= ~INTR_EINT0_TMR0; //disable TIMER0 interrupt | 77 | /* disable TIMER0 interrupt */ |
78 | bitclr16(&IO_INTC_EINT0, INTR_EINT0_TMR0); | ||
78 | 79 | ||
79 | IO_INTC_IRQ0 = INTR_IRQ0_TMR0; //clear TIMER0 interrupt | 80 | /* clear TIMER0 interrupt */ |
81 | IO_INTC_IRQ0 = INTR_IRQ0_TMR0; | ||
80 | 82 | ||
81 | IO_TIMER0_TMMD = CONFIG_TIMER0_TMMD_STOP; | 83 | IO_TIMER0_TMMD = CONFIG_TIMER0_TMMD_STOP; |
82 | 84 | ||
83 | IO_CLK_MOD2 &= ~CLK_MOD2_TMR0; //disable TIMER0 clock | 85 | /* disable TIMER0 clock */ |
86 | bitclr16(&IO_CLK_MOD2, CLK_MOD2_TMR0); | ||
84 | } | 87 | } |
85 | 88 | ||
86 | bool timer_start(void) | 89 | bool timer_start(void) |
@@ -89,12 +92,14 @@ bool timer_start(void) | |||
89 | 92 | ||
90 | stop_timer(); | 93 | stop_timer(); |
91 | 94 | ||
92 | IO_CLK_MOD2 |= CLK_MOD2_TMR0; //enable TIMER0 clock!!!!!!!!! | 95 | /* enable TIMER0 clock */ |
96 | bitset16(&IO_CLK_MOD2, CLK_MOD2_TMR0); | ||
93 | 97 | ||
94 | /* Turn Timer0 to Free Run mode */ | 98 | /* Turn Timer0 to Free Run mode */ |
95 | IO_TIMER0_TMMD = CONFIG_TIMER0_TMMD_FREE_RUN; | 99 | IO_TIMER0_TMMD = CONFIG_TIMER0_TMMD_FREE_RUN; |
96 | 100 | ||
97 | IO_INTC_EINT0 |= INTR_EINT0_TMR0; //enable TIMER0 interrupt | 101 | /* enable TIMER0 interrupt */ |
102 | bitset16(&IO_INTC_EINT0, INTR_EINT0_TMR0); | ||
98 | 103 | ||
99 | restore_interrupt(oldstatus); | 104 | restore_interrupt(oldstatus); |
100 | 105 | ||
diff --git a/firmware/target/arm/tms320dm320/uart-dm320.c b/firmware/target/arm/tms320dm320/uart-dm320.c index 50e6998e2a..0aeb856027 100644 --- a/firmware/target/arm/tms320dm320/uart-dm320.c +++ b/firmware/target/arm/tms320dm320/uart-dm320.c | |||
@@ -39,7 +39,7 @@ static volatile int uart1_receive_count, uart1_receive_read, uart1_receive_write | |||
39 | void uart_init(void) | 39 | void uart_init(void) |
40 | { | 40 | { |
41 | /* Enable UART clock */ | 41 | /* Enable UART clock */ |
42 | IO_CLK_MOD2 |= CLK_MOD2_UART1; | 42 | bitset16(&IO_CLK_MOD2, CLK_MOD2_UART1); |
43 | 43 | ||
44 | // 8-N-1 | 44 | // 8-N-1 |
45 | IO_UART1_MSR = 0xC400; | 45 | IO_UART1_MSR = 0xC400; |
@@ -58,7 +58,7 @@ void uart_init(void) | |||
58 | uart1_send_write=0; | 58 | uart1_send_write=0; |
59 | 59 | ||
60 | /* Enable the interrupt */ | 60 | /* Enable the interrupt */ |
61 | IO_INTC_EINT0 |= INTR_EINT0_UART1; | 61 | bitset16(&IO_INTC_EINT0, INTR_EINT0_UART1); |
62 | } | 62 | } |
63 | 63 | ||
64 | /* This function is not interrupt driven */ | 64 | /* This function is not interrupt driven */ |
@@ -85,7 +85,7 @@ void uart1_puts(const char *str, int size) | |||
85 | memcpy(uart1_send_buffer_ring, str, size); | 85 | memcpy(uart1_send_buffer_ring, str, size); |
86 | 86 | ||
87 | /* Disable interrupt while modifying the pointers */ | 87 | /* Disable interrupt while modifying the pointers */ |
88 | IO_INTC_EINT0 &= ~INTR_EINT0_UART1; | 88 | bitclr16(&IO_INTC_EINT0, INTR_EINT0_UART1); |
89 | 89 | ||
90 | uart1_send_count=size; | 90 | uart1_send_count=size; |
91 | uart1_send_read=0; | 91 | uart1_send_read=0; |
@@ -98,25 +98,27 @@ void uart1_puts(const char *str, int size) | |||
98 | } | 98 | } |
99 | 99 | ||
100 | /* Enable interrupt */ | 100 | /* Enable interrupt */ |
101 | IO_INTC_EINT0 |= INTR_EINT0_UART1; | 101 | bitset16(&IO_INTC_EINT0, INTR_EINT0_UART1); |
102 | } | 102 | } |
103 | 103 | ||
104 | void uart1_clear_queue(void) | 104 | void uart1_clear_queue(void) |
105 | { | 105 | { |
106 | /* Disable interrupt while modifying the pointers */ | 106 | /* Disable interrupt while modifying the pointers */ |
107 | IO_INTC_EINT0 &= ~INTR_EINT0_UART1; | 107 | bitclr16(&IO_INTC_EINT0, INTR_EINT0_UART1); |
108 | |||
108 | uart1_receive_write=0; | 109 | uart1_receive_write=0; |
109 | uart1_receive_count=0; | 110 | uart1_receive_count=0; |
110 | uart1_receive_read=0; | 111 | uart1_receive_read=0; |
112 | |||
111 | /* Enable interrupt */ | 113 | /* Enable interrupt */ |
112 | IO_INTC_EINT0 |= INTR_EINT0_UART1; | 114 | bitset16(&IO_INTC_EINT0, INTR_EINT0_UART1); |
113 | } | 115 | } |
114 | 116 | ||
115 | /* This function returns the number of bytes left in the queue after a read is done (negative if fail)*/ | 117 | /* This function returns the number of bytes left in the queue after a read is done (negative if fail)*/ |
116 | int uart1_gets_queue(char *str, int size) | 118 | int uart1_gets_queue(char *str, int size) |
117 | { | 119 | { |
118 | /* Disable the interrupt while modifying the pointers */ | 120 | /* Disable the interrupt while modifying the pointers */ |
119 | IO_INTC_EINT0 &= ~INTR_EINT0_UART1; | 121 | bitclr16(&IO_INTC_EINT0, INTR_EINT0_UART1); |
120 | int retval; | 122 | int retval; |
121 | 123 | ||
122 | if(uart1_receive_count<size) | 124 | if(uart1_receive_count<size) |
@@ -146,7 +148,7 @@ int uart1_gets_queue(char *str, int size) | |||
146 | } | 148 | } |
147 | 149 | ||
148 | /* Enable the interrupt */ | 150 | /* Enable the interrupt */ |
149 | IO_INTC_EINT0 |= INTR_EINT0_UART1; | 151 | bitset16(&IO_INTC_EINT0, INTR_EINT0_UART1); |
150 | 152 | ||
151 | return retval; | 153 | return retval; |
152 | } | 154 | } |
@@ -176,3 +178,4 @@ void UART1(void) | |||
176 | uart1_send_count--; | 178 | uart1_send_count--; |
177 | } | 179 | } |
178 | } | 180 | } |
181 | |||