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author | Solomon Peachy <pizza@shaftnet.org> | 2020-08-28 11:17:32 -0400 |
---|---|---|
committer | Solomon Peachy <pizza@shaftnet.org> | 2020-08-28 15:19:07 +0000 |
commit | 4a6d8e91bbb1abf7ae59affb2d5a105b6e481344 (patch) | |
tree | 0557047fccef5081bc46a5c282552369ed3c19ff | |
parent | 77019c2c3c72cd7f0b6e716dd66a6e0d7bb21e04 (diff) | |
download | rockbox-4a6d8e91bbb1abf7ae59affb2d5a105b6e481344.tar.gz rockbox-4a6d8e91bbb1abf7ae59affb2d5a105b6e481344.zip |
jz4740: Timer not re-enabled properly
(same fix as g#2703 for the jz4760)
Change-Id: Ic6467d9e6085e3057528b6d1a08b7c07e9dceab4
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/timer-jz4740.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/timer-jz4740.c b/firmware/target/mips/ingenic_jz47xx/timer-jz4740.c index 538547041d..b3f0f71aa3 100644 --- a/firmware/target/mips/ingenic_jz47xx/timer-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/timer-jz4740.c | |||
@@ -18,7 +18,7 @@ | |||
18 | * KIND, either express or implied. | 18 | * KIND, either express or implied. |
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | 21 | ||
22 | #include "config.h" | 22 | #include "config.h" |
23 | #include "jz4740.h" | 23 | #include "jz4740.h" |
24 | #include "system.h" | 24 | #include "system.h" |
@@ -61,7 +61,7 @@ bool timer_set(long cycles, bool start) | |||
61 | { | 61 | { |
62 | __tcu_disable_pwm_output(1); | 62 | __tcu_disable_pwm_output(1); |
63 | 63 | ||
64 | __tcu_mask_half_match_irq(1); | 64 | __tcu_mask_half_match_irq(1); |
65 | __tcu_unmask_full_match_irq(1); | 65 | __tcu_unmask_full_match_irq(1); |
66 | 66 | ||
67 | /* EXTAL clock = CFG_EXTAL (12Mhz in most targets) */ | 67 | /* EXTAL clock = CFG_EXTAL (12Mhz in most targets) */ |
@@ -78,10 +78,10 @@ bool timer_set(long cycles, bool start) | |||
78 | if(start) | 78 | if(start) |
79 | { | 79 | { |
80 | system_enable_irq(IRQ_TCU1); | 80 | system_enable_irq(IRQ_TCU1); |
81 | __tcu_start_counter(1); | ||
82 | } | 81 | } |
83 | 82 | ||
84 | restore_irq(old_irq); | 83 | restore_irq(old_irq); |
84 | __tcu_start_counter(1); | ||
85 | 85 | ||
86 | return true; | 86 | return true; |
87 | } | 87 | } |