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| author | Linus Nielsen Feltzing <linus@haxx.se> | 2002-04-20 22:42:00 +0000 |
|---|---|---|
| committer | Linus Nielsen Feltzing <linus@haxx.se> | 2002-04-20 22:42:00 +0000 |
| commit | 432ba31511bc1a00803657b4b4c60f27791608ba (patch) | |
| tree | 4f29d0c34c94f3029dd96ba3bc74de49e2785e4d | |
| parent | 8c1d94fb235d69c5a61798b9f62d6b6663e738bc (diff) | |
| download | rockbox-432ba31511bc1a00803657b4b4c60f27791608ba.tar.gz rockbox-432ba31511bc1a00803657b4b4c60f27791608ba.zip | |
Changed DMA TCRx register names to DTCRx
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@155 a1c6a512-1295-4272-9138-f99709370657
| -rw-r--r-- | firmware/sh7034.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/firmware/sh7034.h b/firmware/sh7034.h index 25bfcfa4a4..5fca9f51fd 100644 --- a/firmware/sh7034.h +++ b/firmware/sh7034.h | |||
| @@ -96,19 +96,19 @@ | |||
| 96 | #define SAR0_ADDR 0x05FFFF40 | 96 | #define SAR0_ADDR 0x05FFFF40 |
| 97 | #define DAR0_ADDR 0x05FFFF44 | 97 | #define DAR0_ADDR 0x05FFFF44 |
| 98 | #define OR_ADDR 0x05FFFF48 | 98 | #define OR_ADDR 0x05FFFF48 |
| 99 | #define TCR0_ADDR 0x05FFFF4A | 99 | #define DTCR0_ADDR 0x05FFFF4A |
| 100 | #define CHCR0_ADDR 0x05FFFF4E | 100 | #define CHCR0_ADDR 0x05FFFF4E |
| 101 | #define SAR1_ADDR 0x05FFFF50 | 101 | #define SAR1_ADDR 0x05FFFF50 |
| 102 | #define DAR1_ADDR 0x05FFFF54 | 102 | #define DAR1_ADDR 0x05FFFF54 |
| 103 | #define TCR1_ADDR 0x05FFFF5A | 103 | #define DTCR1_ADDR 0x05FFFF5A |
| 104 | #define CHCR1_ADDR 0x05FFFF5E | 104 | #define CHCR1_ADDR 0x05FFFF5E |
| 105 | #define SAR2_ADDR 0x05FFFF60 | 105 | #define SAR2_ADDR 0x05FFFF60 |
| 106 | #define DAR2_ADDR 0x05FFFF64 | 106 | #define DAR2_ADDR 0x05FFFF64 |
| 107 | #define TCR2_ADDR 0x05FFFF6A | 107 | #define DTCR2_ADDR 0x05FFFF6A |
| 108 | #define CHCR2_ADDR 0x05FFFF6E | 108 | #define CHCR2_ADDR 0x05FFFF6E |
| 109 | #define SAR3_ADDR 0x05FFFF70 | 109 | #define SAR3_ADDR 0x05FFFF70 |
| 110 | #define DAR3_ADDR 0x05FFFF74 | 110 | #define DAR3_ADDR 0x05FFFF74 |
| 111 | #define TCR3_ADDR 0x05FFFF7A | 111 | #define DTCR3_ADDR 0x05FFFF7A |
| 112 | #define CHCR3_ADDR 0x05FFFF7E | 112 | #define CHCR3_ADDR 0x05FFFF7E |
| 113 | 113 | ||
| 114 | #define IPRA_ADDR 0x05FFFF84 | 114 | #define IPRA_ADDR 0x05FFFF84 |
| @@ -232,19 +232,19 @@ | |||
| 232 | #define SAR0 (*((volatile unsigned long*)SAR0_ADDR)) | 232 | #define SAR0 (*((volatile unsigned long*)SAR0_ADDR)) |
| 233 | #define DAR0 (*((volatile unsigned long*)DAR0_ADDR)) | 233 | #define DAR0 (*((volatile unsigned long*)DAR0_ADDR)) |
| 234 | #define DMAOR (*((volatile unsigned long*)DMAOR_ADDR)) | 234 | #define DMAOR (*((volatile unsigned long*)DMAOR_ADDR)) |
| 235 | #define TCR0 (*((volatile unsigned long*)TCR0_ADDR)) | 235 | #define DTCR0 (*((volatile unsigned long*)DTCR0_ADDR)) |
| 236 | #define CHCR0 (*((volatile unsigned short*)CHCR0_ADDR)) | 236 | #define CHCR0 (*((volatile unsigned short*)CHCR0_ADDR)) |
| 237 | #define SAR1 (*((volatile unsigned long*)SAR1_ADDR)) | 237 | #define SAR1 (*((volatile unsigned long*)SAR1_ADDR)) |
| 238 | #define DAR1 (*((volatile unsigned long*)DAR1_ADDR)) | 238 | #define DAR1 (*((volatile unsigned long*)DAR1_ADDR)) |
| 239 | #define TCR1 (*((volatile unsigned long*)TCR1_ADDR)) | 239 | #define DTCR1 (*((volatile unsigned long*)DTCR1_ADDR)) |
| 240 | #define CHCR1 (*((volatile unsigned short*)CHCR1_ADDR)) | 240 | #define CHCR1 (*((volatile unsigned short*)CHCR1_ADDR)) |
| 241 | #define SAR2 (*((volatile unsigned long*)SAR2_ADDR)) | 241 | #define SAR2 (*((volatile unsigned long*)SAR2_ADDR)) |
| 242 | #define DAR2 (*((volatile unsigned long*)DAR2_ADDR)) | 242 | #define DAR2 (*((volatile unsigned long*)DAR2_ADDR)) |
| 243 | #define TCR2 (*((volatile unsigned long*)TCR2_ADDR)) | 243 | #define DTCR2 (*((volatile unsigned long*)DTCR2_ADDR)) |
| 244 | #define HCR2 (*((volatile unsigned short*)CHCR2_ADDR)) | 244 | #define HCR2 (*((volatile unsigned short*)CHCR2_ADDR)) |
| 245 | #define SAR3 (*((volatile unsigned long*)SAR3_ADDR)) | 245 | #define SAR3 (*((volatile unsigned long*)SAR3_ADDR)) |
| 246 | #define DAR3 (*((volatile unsigned long*)DAR3_ADDR)) | 246 | #define DAR3 (*((volatile unsigned long*)DAR3_ADDR)) |
| 247 | #define TCR3 (*((volatile unsigned long*)TCR3_ADDR)) | 247 | #define DTCR3 (*((volatile unsigned long*)DTCR3_ADDR)) |
| 248 | #define CHCR3 (*((volatile unsigned short*)CHCR3_ADDR)) | 248 | #define CHCR3 (*((volatile unsigned short*)CHCR3_ADDR)) |
| 249 | 249 | ||
| 250 | #define IPRA (*((volatile unsigned short*)IPRA_ADDR)) | 250 | #define IPRA (*((volatile unsigned short*)IPRA_ADDR)) |