summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorLinus Nielsen Feltzing <linus@haxx.se>2007-11-20 07:17:46 +0000
committerLinus Nielsen Feltzing <linus@haxx.se>2007-11-20 07:17:46 +0000
commit3e192a616d4a672d4d3a1d8159d7088006a49320 (patch)
treec31b8a23dda2f751dc0ba0bdfe4bc6041c776bad
parent4c4c9f27b608afa097731bdad1ac2c597c867349 (diff)
downloadrockbox-3e192a616d4a672d4d3a1d8159d7088006a49320.tar.gz
rockbox-3e192a616d4a672d4d3a1d8159d7088006a49320.zip
Code police raid
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15717 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/target/arm/tms320dm320/dsp-dm320.c198
1 files changed, 102 insertions, 96 deletions
diff --git a/firmware/target/arm/tms320dm320/dsp-dm320.c b/firmware/target/arm/tms320dm320/dsp-dm320.c
index 24c0145a01..e90e05c8f4 100644
--- a/firmware/target/arm/tms320dm320/dsp-dm320.c
+++ b/firmware/target/arm/tms320dm320/dsp-dm320.c
@@ -25,123 +25,129 @@
25 25
26/* A "DSP image" is an array of these, terminated by raw_data_size_half = 0. */ 26/* A "DSP image" is an array of these, terminated by raw_data_size_half = 0. */
27struct dsp_section { 27struct dsp_section {
28 const unsigned short *raw_data; 28 const unsigned short *raw_data;
29 unsigned short physical_addr; 29 unsigned short physical_addr;
30 unsigned short raw_data_size_half; 30 unsigned short raw_data_size_half;
31}; 31};
32 32
33/* Must define struct dsp_section before including the image. */ 33/* Must define struct dsp_section before including the image. */
34#include "dsp_image_helloworld.h" 34#include "dsp_image_helloworld.h"
35 35
36#ifdef DEBUG 36#ifdef DEBUG
37static void dsp_status(void) { 37static void dsp_status(void)
38 unsigned short hpib_ctl = IO_DSPC_HPIB_CONTROL; 38{
39 unsigned short hpib_stat = IO_DSPC_HPIB_STATUS; 39 unsigned short hpib_ctl = IO_DSPC_HPIB_CONTROL;
40 char buffer1[80], buffer2[80]; 40 unsigned short hpib_stat = IO_DSPC_HPIB_STATUS;
41 char buffer1[80], buffer2[80];
41 42
42 DEBUGF("dsp_status(): clkc_hpib=%u clkc_dsp=%u", 43 DEBUGF("dsp_status(): clkc_hpib=%u clkc_dsp=%u",
43 !!(IO_CLK_MOD0 & (1 << 11)), !!(IO_CLK_MOD0 & (1 << 10))); 44 !!(IO_CLK_MOD0 & (1 << 11)), !!(IO_CLK_MOD0 & (1 << 10)));
44 45
45 DEBUGF("dsp_status(): irq_dsphint=%u 7fff=%04x scratch_status=%04x" 46 DEBUGF("dsp_status(): irq_dsphint=%u 7fff=%04x scratch_status=%04x"
46 " acked=%04x", 47 " acked=%04x",
47 (IO_INTC_IRQ0 >> IRQ_DSPHINT) & 1, DSP_(0x7fff), DSP_(_status), 48 (IO_INTC_IRQ0 >> IRQ_DSPHINT) & 1, DSP_(0x7fff), DSP_(_status),
48 DSP_(_acked)); 49 DSP_(_acked));
49#define B(f,w,b,m) if ((w & (1 << b)) == 0) \ 50#define B(f,w,b,m) if ((w & (1 << b)) == 0) \
50 strcat(f, "!"); \ 51 strcat(f, "!"); \
51 strcat(f, #m "|"); 52 strcat(f, #m "|");
52 strcpy(buffer1, ""); 53 strcpy(buffer1, "");
53 B(buffer1, hpib_ctl, 0, EN); 54 B(buffer1, hpib_ctl, 0, EN);
54 B(buffer1, hpib_ctl, 3, NMI); 55 B(buffer1, hpib_ctl, 3, NMI);
55 B(buffer1, hpib_ctl, 5, EXCHG); 56 B(buffer1, hpib_ctl, 5, EXCHG);
56 B(buffer1, hpib_ctl, 7, DINT0); 57 B(buffer1, hpib_ctl, 7, DINT0);
57 B(buffer1, hpib_ctl, 8, DRST); 58 B(buffer1, hpib_ctl, 8, DRST);
58 B(buffer1, hpib_ctl, 9, DHOLD); 59 B(buffer1, hpib_ctl, 9, DHOLD);
59 B(buffer1, hpib_ctl, 10, BIO); 60 B(buffer1, hpib_ctl, 10, BIO);
60 61
61 strcpy(buffer2, ""); 62 strcpy(buffer2, "");
62 B(buffer2, hpib_stat, 8, HOLDA); 63 B(buffer2, hpib_stat, 8, HOLDA);
63 B(buffer2, hpib_stat, 12, DXF); 64 B(buffer2, hpib_stat, 12, DXF);
64 65
65 DEBUGF("dsp_status(): hpib: ctl=%s stat=%s", buffer1, buffer2); 66 DEBUGF("dsp_status(): hpib: ctl=%s stat=%s", buffer1, buffer2);
66#undef B 67#undef B
67} 68}
68#endif 69#endif
69 70
70static void dsp_reset(void) { 71static void dsp_reset(void)
71 DSP_(0x7fff) = 0xdead; 72{
73 DSP_(0x7fff) = 0xdead;
72 74
73 IO_DSPC_HPIB_CONTROL &= ~(1 << 8); 75 IO_DSPC_HPIB_CONTROL &= ~(1 << 8);
74 /* HPIB bus cycles will lock up the ARM in here. Don't touch DSP RAM. */ 76 /* HPIB bus cycles will lock up the ARM in here. Don't touch DSP RAM. */
75 nop; nop; 77 nop; nop;
76 IO_DSPC_HPIB_CONTROL |= 1 << 8; 78 IO_DSPC_HPIB_CONTROL |= 1 << 8;
77 79
78 /* TODO: Timeout. */ 80 /* TODO: Timeout. */
79 while (DSP_(0x7fff) != 0); 81 while (DSP_(0x7fff) != 0);
80} 82}
81 83
82void dsp_wake(void) { 84void dsp_wake(void)
83 /* If this is called concurrently, we may overlap setting and resetting the 85{
84 bit, which causes lost interrupts to the DSP. */ 86 /* If this is called concurrently, we may overlap setting and resetting the
85 int old_level = set_irq_level(IRQ_DISABLED); 87 bit, which causes lost interrupts to the DSP. */
86 88 int old_level = set_irq_level(IRQ_DISABLED);
87 /* The first time you INT0 the DSP, the ROM loader will branch to your RST 89
88 handler. Subsequent times, your INT0 handler will get executed. */ 90 /* The first time you INT0 the DSP, the ROM loader will branch to your RST
89 IO_DSPC_HPIB_CONTROL &= ~(1 << 7); 91 handler. Subsequent times, your INT0 handler will get executed. */
90 nop; nop; 92 IO_DSPC_HPIB_CONTROL &= ~(1 << 7);
91 IO_DSPC_HPIB_CONTROL |= 1 << 7; 93 nop; nop;
92 94 IO_DSPC_HPIB_CONTROL |= 1 << 7;
93 set_irq_level(old_level); 95
96 set_irq_level(old_level);
94} 97}
95 98
96static void dsp_load(const struct dsp_section *im) { 99static void dsp_load(const struct dsp_section *im)
97 while (im->raw_data_size_half) { 100{
98 volatile unsigned short *data_ptr = &DSP_(im->physical_addr); 101 while (im->raw_data_size_half) {
99 unsigned int i; 102 volatile unsigned short *data_ptr = &DSP_(im->physical_addr);
100 103 unsigned int i;
101 /* Use 16-bit writes. */ 104
102 if (im->raw_data) { 105 /* Use 16-bit writes. */
103 DEBUGF("dsp_load(): loading %u words at 0x%04x (0x%08lx)", 106 if (im->raw_data) {
104 im->raw_data_size_half, im->physical_addr, 107 DEBUGF("dsp_load(): loading %u words at 0x%04x (0x%08lx)",
105 (unsigned long)data_ptr); 108 im->raw_data_size_half, im->physical_addr,
106 109 (unsigned long)data_ptr);
107 for (i = 0; i < im->raw_data_size_half; i++) { 110
108 data_ptr[i] = im->raw_data[i]; 111 for (i = 0; i < im->raw_data_size_half; i++) {
109 } 112 data_ptr[i] = im->raw_data[i];
110 } else { 113 }
111 DEBUGF("dsp_load(): clearing %u words at 0x%04x (0x%08lx)", 114 } else {
112 im->raw_data_size_half, im->physical_addr, 115 DEBUGF("dsp_load(): clearing %u words at 0x%04x (0x%08lx)",
113 (unsigned long)data_ptr); 116 im->raw_data_size_half, im->physical_addr,
114 117 (unsigned long)data_ptr);
115 for (i = 0; i < im->raw_data_size_half; i++) { 118
116 data_ptr[i] = 0; 119 for (i = 0; i < im->raw_data_size_half; i++) {
117 } 120 data_ptr[i] = 0;
118 } 121 }
119 122 }
120 im++; 123
121 } 124 im++;
125 }
122} 126}
123 127
124void dsp_init(void) { 128void dsp_init(void)
125 IO_INTC_IRQ0 = 1 << 11; 129{
126 IO_INTC_EINT0 |= 1 << 11; 130 IO_INTC_IRQ0 = 1 << 11;
127 131 IO_INTC_EINT0 |= 1 << 11;
128 dsp_reset(); 132
129 dsp_load(dsp_image_helloworld); 133 dsp_reset();
134 dsp_load(dsp_image_helloworld);
130} 135}
131 136
132void DSPHINT(void) { 137void DSPHINT(void)
133 unsigned int i; 138{
134 char buffer[80]; 139 unsigned int i;
135 140 char buffer[80];
136 IO_INTC_IRQ0 = 1 << 11; 141
137 142 IO_INTC_IRQ0 = 1 << 11;
138 /* DSP stores one character per word. */ 143
139 for (i = 0; i < sizeof(buffer); i++) { 144 /* DSP stores one character per word. */
140 buffer[i] = (&DSP_(_status))[i]; 145 for (i = 0; i < sizeof(buffer); i++) {
141 } 146 buffer[i] = (&DSP_(_status))[i];
142 147 }
143 /* Release shared area to DSP. */ 148
144 dsp_wake(); 149 /* Release shared area to DSP. */
145 150 dsp_wake();
146 DEBUGF("DSP: %s", buffer); 151
152 DEBUGF("DSP: %s", buffer);
147} 153}