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author | William Wilgus <wilgus.william@gmail.com> | 2020-09-13 13:29:00 -0400 |
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committer | William Wilgus <wilgus.william@gmail.com> | 2020-09-13 13:29:00 -0400 |
commit | 3c2b6809d94adcb958c135ca471a666c15fd0060 (patch) | |
tree | acd6cb6018cf42c5a59b56c385c26a87b30503d8 | |
parent | c62493e98adfd27c16eb2adb2ecd22716813b705 (diff) | |
download | rockbox-3c2b6809d94adcb958c135ca471a666c15fd0060.tar.gz rockbox-3c2b6809d94adcb958c135ca471a666c15fd0060.zip |
Xduoo X3 no ADC after ROLO
Speachy suggested we don't shut down the adc on ROLO
this fixes the random adc drop out on ROLO
Change-Id: Ife7d679ce51a6f767963210ee650815f1de12223
-rw-r--r-- | firmware/rolo.c | 2 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/xduoo_x3/sadc-xduoo_x3.c | 6 |
2 files changed, 8 insertions, 0 deletions
diff --git a/firmware/rolo.c b/firmware/rolo.c index e60af46704..7cded0906f 100644 --- a/firmware/rolo.c +++ b/firmware/rolo.c | |||
@@ -286,7 +286,9 @@ int rolo_load(const char* filename) | |||
286 | lcd_remote_puts(0, 1, "Executing"); | 286 | lcd_remote_puts(0, 1, "Executing"); |
287 | lcd_remote_update(); | 287 | lcd_remote_update(); |
288 | #endif | 288 | #endif |
289 | #if (CONFIG_KEYPAD != XDUOO_X3_PAD) /* X3 adc hangs on ROLO */ | ||
289 | adc_close(); | 290 | adc_close(); |
291 | #endif | ||
290 | #if CONFIG_CPU == AS3525v2 | 292 | #if CONFIG_CPU == AS3525v2 |
291 | /* Set CVDD1 power supply to default*/ | 293 | /* Set CVDD1 power supply to default*/ |
292 | ascodec_write_pmu(0x17, 1, 0); | 294 | ascodec_write_pmu(0x17, 1, 0); |
diff --git a/firmware/target/mips/ingenic_jz47xx/xduoo_x3/sadc-xduoo_x3.c b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/sadc-xduoo_x3.c index 0d251754dd..0db1bada9b 100644 --- a/firmware/target/mips/ingenic_jz47xx/xduoo_x3/sadc-xduoo_x3.c +++ b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/sadc-xduoo_x3.c | |||
@@ -260,6 +260,12 @@ int _battery_voltage(void) | |||
260 | void adc_init(void) | 260 | void adc_init(void) |
261 | { | 261 | { |
262 | bat_val = ADC_MASK; | 262 | bat_val = ADC_MASK; |
263 | /* don't re-init*/ | ||
264 | if (!(REG_CPM_CLKGR0 & CLKGR0_SADC) && !(REG_SADC_ADENA & ADENA_POWER)) | ||
265 | { | ||
266 | system_enable_irq(IRQ_SADC); | ||
267 | return; | ||
268 | } | ||
263 | 269 | ||
264 | __cpm_start_sadc(); | 270 | __cpm_start_sadc(); |
265 | mdelay(20); | 271 | mdelay(20); |