as3525v2: adjustable CPU freq : CGU_PROC is identical to as3525 after all

Instead of modifying CGU_PROC to get 24MHz pclk, just switch to fastbus else Clip+ wouldn't boot
Tested on fuzev1/Clip+

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25413 a1c6a512-1295-4272-9138-f99709370657

5 files changed, 12 insertions, 18 deletions

diff --git a/firmware/export/config/sansaclipplus.h b/firmware/export/config/sansaclipplus.h
index 462c0a76e8..76be3cae7f 100644
--- a/firmware/export/config/sansaclipplus.h
+++ b/firmware/export/config/sansaclipplus.h
@@ -161,7 +161,7 @@
 #define ROM_START 0x00000000
 
 /* Define this to the CPU frequency */
-#define CPU_FREQ      250000000
+#define CPU_FREQ      240000000
 
 /* Type of LCD */
 #define CONFIG_LCD LCD_SSD1303
@@ -188,7 +188,7 @@
 #define CONFIG_LED LED_VIRTUAL
 
 /* Define this if you have adjustable CPU frequency */
-//#define HAVE_ADJUSTABLE_CPU_FREQ
+#define HAVE_ADJUSTABLE_CPU_FREQ
 
 #define BOOTFILE_EXT    "sansa"
 #define BOOTFILE        "rockbox." BOOTFILE_EXT
diff --git a/firmware/export/config/sansaclipv2.h b/firmware/export/config/sansaclipv2.h
index 20196dc72f..1736d6fe12 100644
--- a/firmware/export/config/sansaclipv2.h
+++ b/firmware/export/config/sansaclipv2.h
@@ -157,7 +157,7 @@
 #define ROM_START 0x00000000
 
 /* Define this to the CPU frequency */
-#define CPU_FREQ      250000000
+#define CPU_FREQ      240000000
 
 /* Type of LCD */
 #define CONFIG_LCD LCD_SSD1303
@@ -184,7 +184,7 @@
 #define CONFIG_LED LED_VIRTUAL
 
 /* Define this if you have adjustable CPU frequency */
-//#define HAVE_ADJUSTABLE_CPU_FREQ
+#define HAVE_ADJUSTABLE_CPU_FREQ
 
 #define BOOTFILE_EXT    "sansa"
 #define BOOTFILE        "rockbox." BOOTFILE_EXT
diff --git a/firmware/export/config/sansafuzev2.h b/firmware/export/config/sansafuzev2.h
index 3a46003361..fcb4a676d3 100644
--- a/firmware/export/config/sansafuzev2.h
+++ b/firmware/export/config/sansafuzev2.h
@@ -165,7 +165,7 @@
 #define CURRENT_RECORD     CURRENT_NORMAL
 
 /* Define this to the CPU frequency */
-#define CPU_FREQ      250000000
+#define CPU_FREQ      240000000
 
 /* Type of LCD */
 #define CONFIG_LCD LCD_FUZE
@@ -196,7 +196,7 @@
 #endif /* !BOOTLOADER */
 
 /* Define this if you have adjustable CPU frequency */
-//#define HAVE_ADJUSTABLE_CPU_FREQ
+#define HAVE_ADJUSTABLE_CPU_FREQ
 
 #define BOOTFILE_EXT    "sansa"
 #define BOOTFILE        "rockbox." BOOTFILE_EXT
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h
index 65fc681d24..9bb20b21ad 100644
--- a/firmware/target/arm/as3525/clock-target.h
+++ b/firmware/target/arm/as3525/clock-target.h
@@ -66,7 +66,6 @@
 #define AS3525_PLLA_FREQ        240000000
 #define AS3525_PLLA_SETTING     0x113B
 
-/* XXX: CGU_PROC seems to be different as well */
 #define AS3525_FCLK_PREDIV      0
 #define AS3525_FCLK_FREQ        AS3525_PLLA_FREQ
 
diff --git a/firmware/target/arm/as3525/system-as3525.c b/firmware/target/arm/as3525/system-as3525.c
index 4e1714b8aa..41cc54301b 100644
--- a/firmware/target/arm/as3525/system-as3525.c
+++ b/firmware/target/arm/as3525/system-as3525.c
@@ -254,11 +254,14 @@ void system_init(void)
     CCU_SCON = 1; /* AHB master's priority configuration :
                      TIC (Test Interface Controller) > DMA > USB > IDE > ARM */
 
-#if CONFIG_CPU == AS3525
-    CGU_PROC = 0;           /* fclk 24 MHz */
-#endif
     CGU_PERI &= ~0x7f;      /* pclk 24 MHz */
 
+    asm volatile(
+        "mrc p15, 0, r0, c1, c0   \n"      /* control register */
+        "bic r0, r0, #3<<30       \n"      /* clears bus bits : sets fastbus */
+        "mcr p15, 0, r0, c1, c0   \n"
+        : : : "r0" );
+
     CGU_PLLASUP = 0;        /* enable PLLA */
     CGU_PLLA = AS3525_PLLA_SETTING;
     while(!(CGU_INTCTRL & (1<<0)));           /* wait until PLLA is locked */
@@ -269,12 +272,10 @@ void system_init(void)
     while(!(CGU_INTCTRL & (1<<1)));           /* wait until PLLB is locked */
 #endif
 
-#if CONFIG_CPU == AS3525
     /*  Set FCLK frequency */
     CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) |
                 (AS3525_FCLK_PREDIV  << 2) |
                  AS3525_FCLK_SEL);
-#endif
 
     /*  Set PCLK frequency */
     CGU_PERI = ((CGU_PERI & ~0x7F)  |       /* reset divider & clksel bits */
@@ -282,12 +283,6 @@ void system_init(void)
                  (AS3525_PCLK_DIV1 << 6) |
                   AS3525_PCLK_SEL);
 
-    asm volatile(
-        "mrc p15, 0, r0, c1, c0   \n"      /* control register */
-        "bic r0, r0, #3<<30       \n"      /* clears bus bits : sets fastbus */
-        "mcr p15, 0, r0, c1, c0   \n"
-        : : : "r0" );
-
 #ifdef BOOTLOADER
     sdram_init();
 #endif  /* BOOTLOADER */