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author | Björn Stenberg <bjorn@haxx.se> | 2009-01-13 14:56:20 +0000 |
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committer | Björn Stenberg <bjorn@haxx.se> | 2009-01-13 14:56:20 +0000 |
commit | 30414d56c9f8b4fc35ac2918c4d22e5e2ded0eb6 (patch) | |
tree | 37ab86d3e76106c2d8defe9e310995a2684ab266 | |
parent | 7bc29086ecc830fef644446843980031d66546d8 (diff) | |
download | rockbox-30414d56c9f8b4fc35ac2918c4d22e5e2ded0eb6.tar.gz rockbox-30414d56c9f8b4fc35ac2918c4d22e5e2ded0eb6.zip |
Reverting parts of r19760 that was mistakenly committed.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19761 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | apps/plugins/SOURCES | 1 | ||||
-rw-r--r-- | firmware/target/coldfire/iriver/system-iriver.c | 156 | ||||
-rw-r--r-- | firmware/target/coldfire/system-target.h | 8 |
3 files changed, 81 insertions, 84 deletions
diff --git a/apps/plugins/SOURCES b/apps/plugins/SOURCES index 8f461f37e2..7d48be60c1 100644 --- a/apps/plugins/SOURCES +++ b/apps/plugins/SOURCES | |||
@@ -151,4 +151,3 @@ superdom.c | |||
151 | #endif /* m:robe 500 */ | 151 | #endif /* m:robe 500 */ |
152 | 152 | ||
153 | md5sum.c | 153 | md5sum.c |
154 | test_boost.c | ||
diff --git a/firmware/target/coldfire/iriver/system-iriver.c b/firmware/target/coldfire/iriver/system-iriver.c index aa24f6ecc9..1916eec0cd 100644 --- a/firmware/target/coldfire/iriver/system-iriver.c +++ b/firmware/target/coldfire/iriver/system-iriver.c | |||
@@ -50,15 +50,22 @@ | |||
50 | */ | 50 | */ |
51 | 51 | ||
52 | #if MEM < 32 | 52 | #if MEM < 32 |
53 | #define MAX_REFRESH_TIMER 54 | 53 | #define MAX_REFRESH_TIMER 59 |
54 | #define NORMAL_REFRESH_TIMER 10 | 54 | #define NORMAL_REFRESH_TIMER 21 |
55 | #define DEFAULT_REFRESH_TIMER 4 | 55 | #define DEFAULT_REFRESH_TIMER 4 |
56 | #else | 56 | #else |
57 | #define MAX_REFRESH_TIMER 26 | 57 | #define MAX_REFRESH_TIMER 29 |
58 | #define NORMAL_REFRESH_TIMER 4 | 58 | #define NORMAL_REFRESH_TIMER 10 |
59 | #define DEFAULT_REFRESH_TIMER 1 | 59 | #define DEFAULT_REFRESH_TIMER 1 |
60 | #endif | 60 | #endif |
61 | 61 | ||
62 | #ifdef IRIVER_H300_SERIES | ||
63 | #define RECALC_DELAYS(f) \ | ||
64 | pcf50606_i2c_recalc_delay(f) | ||
65 | #else | ||
66 | #define RECALC_DELAYS(f) | ||
67 | #endif | ||
68 | |||
62 | #ifdef HAVE_SERIAL | 69 | #ifdef HAVE_SERIAL |
63 | #define BAUD_RATE 57600 | 70 | #define BAUD_RATE 57600 |
64 | #define BAUDRATE_DIV_DEFAULT (CPUFREQ_DEFAULT/(BAUD_RATE*32*2)) | 71 | #define BAUDRATE_DIV_DEFAULT (CPUFREQ_DEFAULT/(BAUD_RATE*32*2)) |
@@ -66,21 +73,6 @@ | |||
66 | #define BAUDRATE_DIV_MAX (CPUFREQ_MAX/(BAUD_RATE*32*2)) | 73 | #define BAUDRATE_DIV_MAX (CPUFREQ_MAX/(BAUD_RATE*32*2)) |
67 | #endif | 74 | #endif |
68 | 75 | ||
69 | static bool pll_initialized = false; | ||
70 | |||
71 | static void init_pll(void) | ||
72 | { | ||
73 | /* Refresh timer for bypass frequency */ | ||
74 | PLLCR &= ~1; /* Bypass mode */ | ||
75 | PLLCR = 0x0189e025 | (PLLCR & 0x70400000); /* set 112 MHz */ | ||
76 | |||
77 | /* Wait until the PLL has locked. This may take up to 10ms! */ | ||
78 | while(!(PLLCR & 0x80000000)) {}; | ||
79 | |||
80 | pll_initialized = true; | ||
81 | } | ||
82 | |||
83 | |||
84 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ | 76 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ |
85 | void set_cpu_frequency (long) __attribute__ ((section (".icode"))); | 77 | void set_cpu_frequency (long) __attribute__ ((section (".icode"))); |
86 | void set_cpu_frequency(long frequency) | 78 | void set_cpu_frequency(long frequency) |
@@ -89,78 +81,84 @@ void cf_set_cpu_frequency (long) __attribute__ ((section (".icode"))); | |||
89 | void cf_set_cpu_frequency(long frequency) | 81 | void cf_set_cpu_frequency(long frequency) |
90 | #endif | 82 | #endif |
91 | { | 83 | { |
92 | if (!pll_initialized) | ||
93 | init_pll(); | ||
94 | |||
95 | switch(frequency) | 84 | switch(frequency) |
96 | { | 85 | { |
97 | case CPUFREQ_MAX: | 86 | case CPUFREQ_MAX: |
98 | CSCR0 = 0x00001180; /* Flash: 4 wait states */ | 87 | DCR = (0x8200 | DEFAULT_REFRESH_TIMER); |
99 | CSCR1 = 0x00001580; /* LCD: 5 wait states */ | 88 | /* Refresh timer for bypass frequency */ |
89 | PLLCR &= ~1; /* Bypass mode */ | ||
90 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); | ||
91 | RECALC_DELAYS(CPUFREQ_MAX); | ||
92 | PLLCR = 0x018ae025 | (PLLCR & 0x70400000); | ||
93 | CSCR0 = 0x00001180; /* Flash: 4 wait states */ | ||
94 | CSCR1 = 0x00001580; /* LCD: 5 wait states */ | ||
100 | #if CONFIG_USBOTG == USBOTG_ISP1362 | 95 | #if CONFIG_USBOTG == USBOTG_ISP1362 |
101 | CSCR3 = 0x00002180; /* USBOTG: 8 wait states */ | 96 | CSCR3 = 0x00002180; /* USBOTG: 8 wait states */ |
102 | #endif | ||
103 | #if CONFIG_RTC == RTC_PCF50606 | ||
104 | pcf50606_i2c_recalc_delay(CPUFREQ_MAX); | ||
105 | #endif | 97 | #endif |
106 | timers_adjust_prescale(CPUFREQ_MAX_MULT, true); | 98 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. |
107 | DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */ | 99 | This may take up to 10ms! */ |
108 | IDECONFIG1 = 0x10100000 | (1 << 13) | (3 << 10); | 100 | timers_adjust_prescale(CPUFREQ_MAX_MULT, true); |
109 | /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ | 101 | DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */ |
110 | IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable 2 + CS2wait */ | 102 | cpu_frequency = CPUFREQ_MAX; |
111 | 103 | IDECONFIG1 = 0x10100000 | (1 << 13) | (3 << 10); | |
112 | PLLCR = (PLLCR & ~0x07000000) | (1 << 24); /* set CPUDIV */ | 104 | /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ |
113 | DCR = (0x8200 | MAX_REFRESH_TIMER); /* DRAM refresh timer */ | 105 | IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */ |
114 | cpu_frequency = CPUFREQ_MAX; | ||
115 | break; | ||
116 | 106 | ||
117 | case CPUFREQ_NORMAL: | 107 | #ifdef HAVE_SERIAL |
118 | PLLCR = (PLLCR & ~0x07000000) | (5 << 24); /* set CPUDIV */ | 108 | UBG10 = BAUDRATE_DIV_MAX >> 8; |
119 | DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* DRAM refresh timer */ | 109 | UBG20 = BAUDRATE_DIV_MAX & 0xff; |
120 | cpu_frequency = CPUFREQ_MAX; | ||
121 | |||
122 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ | ||
123 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | ||
124 | #if CONFIG_USBOTG == USBOTG_ISP1362 | ||
125 | CSCR3 = 0x00000580; /* USBOTG: 1 wait state */ | ||
126 | #endif | 110 | #endif |
127 | #if CONFIG_RTC == RTC_PCF50606 | 111 | break; |
128 | pcf50606_i2c_recalc_delay(CPUFREQ_NORMAL); | 112 | |
113 | case CPUFREQ_NORMAL: | ||
114 | DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER; | ||
115 | /* Refresh timer for bypass frequency */ | ||
116 | PLLCR &= ~1; /* Bypass mode */ | ||
117 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); | ||
118 | RECALC_DELAYS(CPUFREQ_NORMAL); | ||
119 | PLLCR = 0x0589e021 | (PLLCR & 0x70400000); | ||
120 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ | ||
121 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | ||
122 | #if CONFIG_USBOTG == USBOTG_ISP1362 | ||
123 | CSCR3 = 0x00000580; /* USBOTG: 1 wait state */ | ||
129 | #endif | 124 | #endif |
130 | timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true); | 125 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. |
126 | This may take up to 10ms! */ | ||
127 | timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true); | ||
128 | DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */ | ||
129 | cpu_frequency = CPUFREQ_NORMAL; | ||
130 | IDECONFIG1 = 0x10100000 | (1 << 13) | (1 << 10); | ||
131 | /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ | ||
132 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ | ||
131 | 133 | ||
132 | IDECONFIG1 = 0x10100000 | (1 << 13) | (1 << 10); | 134 | #ifdef HAVE_SERIAL |
133 | /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ | 135 | UBG10 = BAUDRATE_DIV_NORMAL >> 8; |
134 | IDECONFIG2 = 0x40000; /* TA enable 2 */ | 136 | UBG20 = BAUDRATE_DIV_NORMAL & 0xff; |
135 | break; | ||
136 | |||
137 | default: | ||
138 | DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER; | ||
139 | /* Refresh timer for bypass frequency */ | ||
140 | PLLCR &= ~1; /* Bypass mode */ | ||
141 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true); | ||
142 | #if CONFIG_RTC == RTC_PCF50606 | ||
143 | pcf50606_i2c_recalc_delay(CPUFREQ_DEFAULT_MULT); | ||
144 | #endif | 137 | #endif |
145 | /* Power down PLL, but keep CRSEL and CLSEL */ | 138 | break; |
146 | PLLCR = 0x00800200 | (PLLCR & 0x70400000); | 139 | default: |
147 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ | 140 | DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER; |
148 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | 141 | /* Refresh timer for bypass frequency */ |
142 | PLLCR &= ~1; /* Bypass mode */ | ||
143 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true); | ||
144 | RECALC_DELAYS(CPUFREQ_DEFAULT); | ||
145 | /* Power down PLL, but keep CRSEL and CLSEL */ | ||
146 | PLLCR = 0x00800200 | (PLLCR & 0x70400000); | ||
147 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ | ||
148 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | ||
149 | #if CONFIG_USBOTG == USBOTG_ISP1362 | 149 | #if CONFIG_USBOTG == USBOTG_ISP1362 |
150 | CSCR3 = 0x00000180; /* USBOTG: 0 wait states */ | 150 | CSCR3 = 0x00000180; /* USBOTG: 0 wait states */ |
151 | #endif | 151 | #endif |
152 | DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ | 152 | DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ |
153 | cpu_frequency = CPUFREQ_DEFAULT; | 153 | cpu_frequency = CPUFREQ_DEFAULT; |
154 | IDECONFIG1 = 0x10100000 | (1 << 13) | (1 << 10); | 154 | IDECONFIG1 = 0x10100000 | (1 << 13) | (1 << 10); |
155 | /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ | 155 | /* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */ |
156 | IDECONFIG2 = 0x40000; /* TA enable 2 */ | 156 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ |
157 | |||
158 | pll_initialized = false; | ||
159 | break; | ||
160 | } | ||
161 | 157 | ||
162 | #ifdef HAVE_SERIAL | 158 | #ifdef HAVE_SERIAL |
163 | UBG10 = BAUDRATE_DIV_NORMAL >> 8; | 159 | UBG10 = BAUDRATE_DIV_DEFAULT >> 8; |
164 | UBG20 = BAUDRATE_DIV_NORMAL & 0xff; | 160 | UBG20 = BAUDRATE_DIV_DEFAULT & 0xff; |
165 | #endif | 161 | #endif |
162 | break; | ||
163 | } | ||
166 | } | 164 | } |
diff --git a/firmware/target/coldfire/system-target.h b/firmware/target/coldfire/system-target.h index 892cbe89cf..84ec6ed4b0 100644 --- a/firmware/target/coldfire/system-target.h +++ b/firmware/target/coldfire/system-target.h | |||
@@ -215,11 +215,11 @@ extern void cf_set_cpu_frequency(long frequency); | |||
215 | /* 11.2896 MHz */ | 215 | /* 11.2896 MHz */ |
216 | #define CPUFREQ_DEFAULT_MULT 1 | 216 | #define CPUFREQ_DEFAULT_MULT 1 |
217 | #define CPUFREQ_DEFAULT (CPUFREQ_DEFAULT_MULT * CPU_FREQ) | 217 | #define CPUFREQ_DEFAULT (CPUFREQ_DEFAULT_MULT * CPU_FREQ) |
218 | /* 22.5792 MHz */ | 218 | /* 45.1584 MHz */ |
219 | #define CPUFREQ_NORMAL_MULT 2 | 219 | #define CPUFREQ_NORMAL_MULT 4 |
220 | #define CPUFREQ_NORMAL (CPUFREQ_NORMAL_MULT * CPU_FREQ) | 220 | #define CPUFREQ_NORMAL (CPUFREQ_NORMAL_MULT * CPU_FREQ) |
221 | /* 112.896 MHz */ | 221 | /* 124.1856 MHz */ |
222 | #define CPUFREQ_MAX_MULT 10 | 222 | #define CPUFREQ_MAX_MULT 11 |
223 | #define CPUFREQ_MAX (CPUFREQ_MAX_MULT * CPU_FREQ) | 223 | #define CPUFREQ_MAX (CPUFREQ_MAX_MULT * CPU_FREQ) |
224 | 224 | ||
225 | #endif /* SYSTEM_TARGET_H */ | 225 | #endif /* SYSTEM_TARGET_H */ |