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authorMiika Pekkarinen <miipekk@ihme.org>2006-11-26 14:50:15 +0000
committerMiika Pekkarinen <miipekk@ihme.org>2006-11-26 14:50:15 +0000
commit2c994b44ba1f8bdba786dd6bb327ec7d24eb1cae (patch)
tree83cac7eaafe1a3b51122438f1cfdbb74b34fe9d9
parentf14f59f9f387964687fda05b3881a090fb7d713d (diff)
downloadrockbox-2c994b44ba1f8bdba786dd6bb327ec7d24eb1cae.tar.gz
rockbox-2c994b44ba1f8bdba786dd6bb327ec7d24eb1cae.zip
Fixed the errors for H300.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11603 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/drivers/eeprom_24cxx.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/firmware/drivers/eeprom_24cxx.c b/firmware/drivers/eeprom_24cxx.c
index 20ad1dfebe..6016c0f841 100644
--- a/firmware/drivers/eeprom_24cxx.c
+++ b/firmware/drivers/eeprom_24cxx.c
@@ -36,6 +36,13 @@
36#define SW_I2C_WRITE 0 36#define SW_I2C_WRITE 0
37#define SW_I2C_READ 1 37#define SW_I2C_READ 1
38 38
39/* Use cache to speedup writing to the chip. */
40static char data_cache[EEPROM_SIZE];
41static uint8_t cached_bitfield[EEPROM_SIZE/8];
42
43#define IS_CACHED(addr) (cached_bitfield[addr/8] & (1 << (addr % 8)))
44#define SET_CACHED(addr) (cached_bitfield[addr/8] |= 1 << (addr % 8))
45
39/* h1x0 needs its own i2c driver, 46/* h1x0 needs its own i2c driver,
40 h3x0 uses the pcf i2c driver */ 47 h3x0 uses the pcf i2c driver */
41 48
@@ -58,10 +65,6 @@
58/* delay loop to achieve 400kHz at 120MHz CPU frequency */ 65/* delay loop to achieve 400kHz at 120MHz CPU frequency */
59#define DELAY do { int _x; for(_x=0;_x<22;_x++);} while(0) 66#define DELAY do { int _x; for(_x=0;_x<22;_x++);} while(0)
60 67
61/* Use cache to speedup writing to the chip. */
62static char data_cache[EEPROM_SIZE];
63static uint8_t cached_bitfield[EEPROM_SIZE/8];
64
65static void sw_i2c_init(void) 68static void sw_i2c_init(void)
66{ 69{
67 logf("sw_i2c_init"); 70 logf("sw_i2c_init");
@@ -288,9 +291,6 @@ void eeprom_24cxx_init(void)
288 memset(cached_bitfield, 0, sizeof cached_bitfield); 291 memset(cached_bitfield, 0, sizeof cached_bitfield);
289} 292}
290 293
291#define IS_CACHED(addr) (cached_bitfield[addr/8] & (1 << (addr % 8)))
292#define SET_CACHED(addr) (cached_bitfield[addr/8] |= 1 << (addr % 8))
293
294int eeprom_24cxx_read_byte(unsigned int address, char *c) 294int eeprom_24cxx_read_byte(unsigned int address, char *c)
295{ 295{
296 int ret; 296 int ret;