diff options
author | Michael Sparmann <theseven@rockbox.org> | 2009-10-05 16:01:26 +0000 |
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committer | Michael Sparmann <theseven@rockbox.org> | 2009-10-05 16:01:26 +0000 |
commit | 271c67e802c65b243c7e4c76e276a893345f15fe (patch) | |
tree | 10e1389be74cfc62c0651a590c4496fb2e1fea34 | |
parent | 79bf2da1ef6f8f16c44ba8fa6d71ea6870a19767 (diff) | |
download | rockbox-271c67e802c65b243c7e4c76e276a893345f15fe.tar.gz rockbox-271c67e802c65b243c7e4c76e276a893345f15fe.zip |
Fix the user timer on iPod Nano 2G
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22959 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/export/s5l8700.h | 6 | ||||
-rw-r--r-- | firmware/target/arm/s5l8700/system-s5l8700.c | 19 | ||||
-rw-r--r-- | firmware/target/arm/s5l8700/timer-s5l8700.c | 20 |
3 files changed, 31 insertions, 14 deletions
diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h index 801e8a0857..f652a62a2e 100644 --- a/firmware/export/s5l8700.h +++ b/firmware/export/s5l8700.h | |||
@@ -126,10 +126,16 @@ | |||
126 | #define INTMOD (*(REG32_PTR_T)(0x39C00004)) /* Interrupt mode register. */ | 126 | #define INTMOD (*(REG32_PTR_T)(0x39C00004)) /* Interrupt mode register. */ |
127 | #define INTMSK (*(REG32_PTR_T)(0x39C00008)) /* Determines which interrupt source is masked. The */ | 127 | #define INTMSK (*(REG32_PTR_T)(0x39C00008)) /* Determines which interrupt source is masked. The */ |
128 | #if CONFIG_CPU==S5L8701 | 128 | #if CONFIG_CPU==S5L8701 |
129 | #define INTMSK_TIMERA (1<<5) | ||
129 | #define INTMSK_TIMERB (1<<5) | 130 | #define INTMSK_TIMERB (1<<5) |
131 | #define INTMSK_TIMERC (1<<5) | ||
132 | #define INTMSK_TIMERD (1<<5) | ||
130 | #define INTMSK_ECC (1<<19) | 133 | #define INTMSK_ECC (1<<19) |
131 | #else | 134 | #else |
135 | #define INTMSK_TIMERA (1<<5) | ||
132 | #define INTMSK_TIMERB (1<<7) | 136 | #define INTMSK_TIMERB (1<<7) |
137 | #define INTMSK_TIMERC (1<<8) | ||
138 | #define INTMSK_TIMERD (1<<9) | ||
133 | #endif | 139 | #endif |
134 | #define PRIORITY (*(REG32_PTR_T)(0x39C0000C)) /* IRQ priority control register */ | 140 | #define PRIORITY (*(REG32_PTR_T)(0x39C0000C)) /* IRQ priority control register */ |
135 | #define INTPND (*(REG32_PTR_T)(0x39C00010)) /* Indicates the interrupt request status. */ | 141 | #define INTPND (*(REG32_PTR_T)(0x39C00010)) /* Indicates the interrupt request status. */ |
diff --git a/firmware/target/arm/s5l8700/system-s5l8700.c b/firmware/target/arm/s5l8700/system-s5l8700.c index 3477bb8886..a557700436 100644 --- a/firmware/target/arm/s5l8700/system-s5l8700.c +++ b/firmware/target/arm/s5l8700/system-s5l8700.c | |||
@@ -64,14 +64,25 @@ default_interrupt(RESERVED2); | |||
64 | default_interrupt(INT_MSTICK); | 64 | default_interrupt(INT_MSTICK); |
65 | default_interrupt(INT_ADC_WAKEUP); | 65 | default_interrupt(INT_ADC_WAKEUP); |
66 | default_interrupt(INT_ADC); | 66 | default_interrupt(INT_ADC); |
67 | default_interrupt(INT_UNK1); | ||
68 | default_interrupt(INT_UNK2); | ||
69 | default_interrupt(INT_UNK3); | ||
67 | 70 | ||
68 | 71 | ||
72 | void INT_TIMER(void) | ||
73 | { | ||
74 | if (TACON & 0x00038000) INT_TIMERA(); | ||
75 | if (TBCON & 0x00038000) INT_TIMERB(); | ||
76 | if (TCCON & 0x00038000) INT_TIMERC(); | ||
77 | if (TDCON & 0x00038000) INT_TIMERD(); | ||
78 | } | ||
79 | |||
69 | 80 | ||
70 | #if CONFIG_CPU==S5L8701 | 81 | #if CONFIG_CPU==S5L8701 |
71 | static void (* const irqvector[])(void) = | 82 | static void (* const irqvector[])(void) = |
72 | { /* still 90% unverified and probably incorrect */ | 83 | { /* still 90% unverified and probably incorrect */ |
73 | EXT0,EXT1,EXT2,EINT_VBUS,EINTG,INT_TIMERB,INT_WDT,INT_TIMERA, | 84 | EXT0,EXT1,EXT2,EINT_VBUS,EINTG,INT_TIMER,INT_WDT,INT_UNK1, |
74 | INT_TIMERC,INT_TIMERD,INT_DMA,INT_ALARM_RTC,INT_PRI_RTC,RESERVED1,INT_UART,INT_USB_HOST, | 85 | INT_UNK2,INT_UNK3,INT_DMA,INT_ALARM_RTC,INT_PRI_RTC,RESERVED1,INT_UART,INT_USB_HOST, |
75 | INT_USB_FUNC,INT_LCDC_0,INT_LCDC_1,INT_CALM,INT_ATA,INT_UART0,INT_SPDIF_OUT,INT_ECC, | 86 | INT_USB_FUNC,INT_LCDC_0,INT_LCDC_1,INT_CALM,INT_ATA,INT_UART0,INT_SPDIF_OUT,INT_ECC, |
76 | INT_SDCI,INT_LCD,INT_SPI,INT_IIC,RESERVED2,INT_MSTICK,INT_ADC_WAKEUP,INT_ADC | 87 | INT_SDCI,INT_LCD,INT_SPI,INT_IIC,RESERVED2,INT_MSTICK,INT_ADC_WAKEUP,INT_ADC |
77 | }; | 88 | }; |
@@ -88,8 +99,8 @@ static void (* const irqvector[])(void) = | |||
88 | #if CONFIG_CPU==S5L8701 | 99 | #if CONFIG_CPU==S5L8701 |
89 | static const char * const irqname[] = | 100 | static const char * const irqname[] = |
90 | { /* still 90% unverified and probably incorrect */ | 101 | { /* still 90% unverified and probably incorrect */ |
91 | "EXT0","EXT1","EXT2","EINT_VBUS","EINTG","INT_TIMERB","INT_WDT","INT_TIMERA", | 102 | "EXT0","EXT1","EXT2","EINT_VBUS","EINTG","INT_TIMER","INT_WDT","INT_UNK1", |
92 | "INT_TIMERC","INT_TIMERD","INT_DMA","INT_ALARM_RTC","INT_PRI_RTC","Reserved","INT_UART","INT_USB_HOST", | 103 | "INT_UNK2","INT_UNK3","INT_DMA","INT_ALARM_RTC","INT_PRI_RTC","Reserved","INT_UART","INT_USB_HOST", |
93 | "INT_USB_FUNC","INT_LCDC_0","INT_LCDC_1","INT_CALM","INT_ATA","INT_UART0","INT_SPDIF_OUT","INT_ECC", | 104 | "INT_USB_FUNC","INT_LCDC_0","INT_LCDC_1","INT_CALM","INT_ATA","INT_UART0","INT_SPDIF_OUT","INT_ECC", |
94 | "INT_SDCI","INT_LCD","INT_SPI","INT_IIC","Reserved","INT_MSTICK","INT_ADC_WAKEUP","INT_ADC" | 105 | "INT_SDCI","INT_LCD","INT_SPI","INT_IIC","Reserved","INT_MSTICK","INT_ADC_WAKEUP","INT_ADC" |
95 | }; | 106 | }; |
diff --git a/firmware/target/arm/s5l8700/timer-s5l8700.c b/firmware/target/arm/s5l8700/timer-s5l8700.c index 3e8e7d7ad4..9ae7e01565 100644 --- a/firmware/target/arm/s5l8700/timer-s5l8700.c +++ b/firmware/target/arm/s5l8700/timer-s5l8700.c | |||
@@ -35,10 +35,10 @@ | |||
35 | TODO: investigate why the timer seems to count twice as fast as expected | 35 | TODO: investigate why the timer seems to count twice as fast as expected |
36 | */ | 36 | */ |
37 | 37 | ||
38 | void INT_TIMERD(void) | 38 | void INT_TIMERC(void) |
39 | { | 39 | { |
40 | /* clear interrupt */ | 40 | /* clear interrupt */ |
41 | TDCON = TDCON; | 41 | TCCON = TCCON; |
42 | 42 | ||
43 | if (pfn_timer != NULL) { | 43 | if (pfn_timer != NULL) { |
44 | pfn_timer(); | 44 | pfn_timer(); |
@@ -52,7 +52,7 @@ bool timer_set(long cycles, bool start) | |||
52 | long count; | 52 | long count; |
53 | 53 | ||
54 | /* stop and clear timer */ | 54 | /* stop and clear timer */ |
55 | TDCMD = (1 << 1); /* TD_CLR */ | 55 | TCCMD = (1 << 1); /* TD_CLR */ |
56 | 56 | ||
57 | /* optionally unregister any previously registered timer user */ | 57 | /* optionally unregister any previously registered timer user */ |
58 | if (start) { | 58 | if (start) { |
@@ -78,27 +78,27 @@ bool timer_set(long cycles, bool start) | |||
78 | } | 78 | } |
79 | 79 | ||
80 | /* configure timer */ | 80 | /* configure timer */ |
81 | TDCON = (1 << 12) | /* TD_INT0_EN */ | 81 | TCCON = (1 << 12) | /* TD_INT0_EN */ |
82 | (cs << 8) | /* TS_CS */ | 82 | (cs << 8) | /* TS_CS */ |
83 | (0 << 4); /* TD_MODE_SEL, 0 = interval mode */ | 83 | (0 << 4); /* TD_MODE_SEL, 0 = interval mode */ |
84 | TDPRE = prescale - 1; | 84 | TCPRE = prescale - 1; |
85 | TDDATA0 = count; | 85 | TCDATA0 = count; |
86 | TDCMD = (1 << 0); /* TD_ENABLE */ | 86 | TCCMD = (1 << 0); /* TD_ENABLE */ |
87 | 87 | ||
88 | /* enable interrupt */ | 88 | /* enable interrupt */ |
89 | INTMSK |= (1 << 9); | 89 | INTMSK |= INTMSK_TIMERC; |
90 | 90 | ||
91 | return true; | 91 | return true; |
92 | } | 92 | } |
93 | 93 | ||
94 | bool timer_start(void) | 94 | bool timer_start(void) |
95 | { | 95 | { |
96 | TDCMD = (1 << 0); /* TD_ENABLE */ | 96 | TCCMD = (1 << 0); /* TD_ENABLE */ |
97 | return true; | 97 | return true; |
98 | } | 98 | } |
99 | 99 | ||
100 | void timer_stop(void) | 100 | void timer_stop(void) |
101 | { | 101 | { |
102 | TDCMD = (0 << 0); /* TD_ENABLE */ | 102 | TCCMD = (0 << 0); /* TD_ENABLE */ |
103 | } | 103 | } |
104 | 104 | ||