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authorAidan MacDonald <amachronic@protonmail.com>2021-12-02 21:31:54 +0000
committerAidan MacDonald <amachronic@protonmail.com>2021-12-02 21:31:54 +0000
commit2512ed1c56a7c415f5a13ac2f38f72278e3ac660 (patch)
treee500f3c7ea491f996fe9c33aaa7ed62b9ca234b7
parent4162a4618426b259c8b87c75c127f6f47b2b7ab0 (diff)
downloadrockbox-2512ed1c56a7c415f5a13ac2f38f72278e3ac660.tar.gz
rockbox-2512ed1c56a7c415f5a13ac2f38f72278e3ac660.zip
Make inline functions in headers 'static inline'
Future-proofing against newer versions of GCC/binutils which are stricter about the use of 'inline' functions in headers. Change-Id: Id620812ed340f0d790ba6c5b8b5cb1d700acfbbf
-rw-r--r--firmware/export/i2c-async.h9
-rw-r--r--firmware/target/mips/ingenic_x1000/clk-x1000.h4
-rw-r--r--firmware/target/mips/ingenic_x1000/sfc-x1000.h4
3 files changed, 9 insertions, 8 deletions
diff --git a/firmware/export/i2c-async.h b/firmware/export/i2c-async.h
index 2877d1875c..f31a73452b 100644
--- a/firmware/export/i2c-async.h
+++ b/firmware/export/i2c-async.h
@@ -247,14 +247,15 @@ extern int i2c_reg_modify1(int bus, uint8_t addr, uint8_t reg,
247 uint8_t clr, uint8_t set, uint8_t* val); 247 uint8_t clr, uint8_t set, uint8_t* val);
248 248
249/* Variant to write a single 8-bit value to a register */ 249/* Variant to write a single 8-bit value to a register */
250inline int i2c_reg_write1(int bus, uint8_t addr, uint8_t reg, uint8_t val) 250static inline int i2c_reg_write1(int bus, uint8_t addr,
251 uint8_t reg, uint8_t val)
251{ 252{
252 return i2c_reg_write(bus, addr, reg, 1, &val); 253 return i2c_reg_write(bus, addr, reg, 1, &val);
253} 254}
254 255
255/* Variant to read an 8-bit value from a register; returns the value 256/* Variant to read an 8-bit value from a register; returns the value
256 * directly, or returns -1 on any error. */ 257 * directly, or returns -1 on any error. */
257inline int i2c_reg_read1(int bus, uint8_t addr, uint8_t reg) 258static inline int i2c_reg_read1(int bus, uint8_t addr, uint8_t reg)
258{ 259{
259 uint8_t v; 260 uint8_t v;
260 int i = i2c_reg_read(bus, addr, reg, 1, &v); 261 int i = i2c_reg_read(bus, addr, reg, 1, &v);
@@ -265,8 +266,8 @@ inline int i2c_reg_read1(int bus, uint8_t addr, uint8_t reg)
265} 266}
266 267
267/* Variant to set or clear one bit in an 8-bit register */ 268/* Variant to set or clear one bit in an 8-bit register */
268inline int i2c_reg_setbit1(int bus, uint8_t addr, uint8_t reg, 269static inline int i2c_reg_setbit1(int bus, uint8_t addr, uint8_t reg,
269 int bit, int value, uint8_t* val) 270 int bit, int value, uint8_t* val)
270{ 271{
271 uint8_t clr = 0, set = 0; 272 uint8_t clr = 0, set = 0;
272 if(value) 273 if(value)
diff --git a/firmware/target/mips/ingenic_x1000/clk-x1000.h b/firmware/target/mips/ingenic_x1000/clk-x1000.h
index e19c56d0ba..f7153da564 100644
--- a/firmware/target/mips/ingenic_x1000/clk-x1000.h
+++ b/firmware/target/mips/ingenic_x1000/clk-x1000.h
@@ -80,13 +80,13 @@ extern void clk_set_ccr_div(uint32_t divbits);
80extern void clk_set_ddr(x1000_clk_t src, uint32_t div); 80extern void clk_set_ddr(x1000_clk_t src, uint32_t div);
81 81
82/* Returns the smallest n such that infreq/n <= outfreq */ 82/* Returns the smallest n such that infreq/n <= outfreq */
83inline uint32_t clk_calc_div(uint32_t infreq, uint32_t outfreq) 83static inline uint32_t clk_calc_div(uint32_t infreq, uint32_t outfreq)
84{ 84{
85 return (infreq + (outfreq - 1)) / outfreq; 85 return (infreq + (outfreq - 1)) / outfreq;
86} 86}
87 87
88/* Returns the smallest n such that (infreq >> n) <= outfreq */ 88/* Returns the smallest n such that (infreq >> n) <= outfreq */
89inline uint32_t clk_calc_shift(uint32_t infreq, uint32_t outfreq) 89static inline uint32_t clk_calc_shift(uint32_t infreq, uint32_t outfreq)
90{ 90{
91 uint32_t div = clk_calc_div(infreq, outfreq); 91 uint32_t div = clk_calc_div(infreq, outfreq);
92 return __builtin_clz(div) ^ 31; 92 return __builtin_clz(div) ^ 31;
diff --git a/firmware/target/mips/ingenic_x1000/sfc-x1000.h b/firmware/target/mips/ingenic_x1000/sfc-x1000.h
index d28bcb6740..afb4aa3ce6 100644
--- a/firmware/target/mips/ingenic_x1000/sfc-x1000.h
+++ b/firmware/target/mips/ingenic_x1000/sfc-x1000.h
@@ -87,13 +87,13 @@ extern void sfc_irq_end(void);
87extern void sfc_set_clock(uint32_t freq); 87extern void sfc_set_clock(uint32_t freq);
88 88
89/* Set the device configuration register */ 89/* Set the device configuration register */
90inline void sfc_set_dev_conf(uint32_t conf) 90static inline void sfc_set_dev_conf(uint32_t conf)
91{ 91{
92 REG_SFC_DEV_CONF = conf; 92 REG_SFC_DEV_CONF = conf;
93} 93}
94 94
95/* Control the state of the write protect pin */ 95/* Control the state of the write protect pin */
96inline void sfc_set_wp_enable(bool en) 96static inline void sfc_set_wp_enable(bool en)
97{ 97{
98 jz_writef(SFC_GLB, WP_EN(en ? 1 : 0)); 98 jz_writef(SFC_GLB, WP_EN(en ? 1 : 0));
99} 99}