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| author | Linus Nielsen Feltzing <linus@haxx.se> | 2005-07-17 15:59:32 +0000 |
|---|---|---|
| committer | Linus Nielsen Feltzing <linus@haxx.se> | 2005-07-17 15:59:32 +0000 |
| commit | 170bb8eb78703bd6f2ae951e2292c89ae7565a29 (patch) | |
| tree | eb1091a3e9af0ea684d85a00638f48b9db46e527 | |
| parent | cd8bfeb8a36197080703a21def84eb2da173d23c (diff) | |
| download | rockbox-170bb8eb78703bd6f2ae951e2292c89ae7565a29.tar.gz rockbox-170bb8eb78703bd6f2ae951e2292c89ae7565a29.zip | |
iriver: Reduced LCD write cycle length to 65ns, almost halving the execution time for lcd_update, from 1.8ms to 1ms in 120MHz
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7181 a1c6a512-1295-4272-9138-f99709370657
| -rw-r--r-- | firmware/system.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/firmware/system.c b/firmware/system.c index 1e42fab9e7..219ad976bc 100644 --- a/firmware/system.c +++ b/firmware/system.c | |||
| @@ -521,7 +521,7 @@ void set_cpu_frequency(long frequency) | |||
| 521 | PLLCR &= ~1; /* Bypass mode */ | 521 | PLLCR &= ~1; /* Bypass mode */ |
| 522 | PLLCR = 0x11853005; | 522 | PLLCR = 0x11853005; |
| 523 | CSCR0 = 0x00000980; /* Flash: 2 wait state */ | 523 | CSCR0 = 0x00000980; /* Flash: 2 wait state */ |
| 524 | CSCR1 = 0x00002580; /* LCD: 9 wait states */ | 524 | CSCR1 = 0x00000980; /* LCD: 2 wait states */ |
| 525 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | 525 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. |
| 526 | This may take up to 10ms! */ | 526 | This may take up to 10ms! */ |
| 527 | DCR = (DCR & ~0x01ff) | MAX_REFRESH_TIMER; /* Refresh timer */ | 527 | DCR = (DCR & ~0x01ff) | MAX_REFRESH_TIMER; /* Refresh timer */ |
| @@ -540,7 +540,7 @@ void set_cpu_frequency(long frequency) | |||
| 540 | PLLCR &= ~1; /* Bypass mode */ | 540 | PLLCR &= ~1; /* Bypass mode */ |
| 541 | PLLCR = 0x10886001; | 541 | PLLCR = 0x10886001; |
| 542 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ | 542 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ |
| 543 | CSCR1 = 0x00000980; /* LCD: 2 wait states */ | 543 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ |
| 544 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | 544 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. |
| 545 | This may take up to 10ms! */ | 545 | This may take up to 10ms! */ |
| 546 | DCR = (DCR & ~0x01ff) | NORMAL_REFRESH_TIMER; /* Refresh timer */ | 546 | DCR = (DCR & ~0x01ff) | NORMAL_REFRESH_TIMER; /* Refresh timer */ |