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author | Jonathan Gordon <rockbox@jdgordon.info> | 2007-02-18 01:17:06 +0000 |
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committer | Jonathan Gordon <rockbox@jdgordon.info> | 2007-02-18 01:17:06 +0000 |
commit | 1083de8e7dd9360c999dbfe08cdf5d7c1ee5c4a6 (patch) | |
tree | 3d7684811452c44a4c499c35341a98bfb66fc814 | |
parent | c2f05592ee1ba8399b64b5f63669c0eaa8cb8e0e (diff) | |
download | rockbox-1083de8e7dd9360c999dbfe08cdf5d7c1ee5c4a6.tar.gz rockbox-1083de8e7dd9360c999dbfe08cdf5d7c1ee5c4a6.zip |
CONFIG_USBOTG fixes
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@12377 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | apps/main.c | 8 | ||||
-rw-r--r-- | firmware/target/coldfire/crt0.S | 2 | ||||
-rw-r--r-- | firmware/target/coldfire/iriver/system-iriver.c | 6 |
3 files changed, 8 insertions, 8 deletions
diff --git a/apps/main.c b/apps/main.c index 6e49b51809..9f521e5064 100644 --- a/apps/main.c +++ b/apps/main.c | |||
@@ -95,11 +95,11 @@ | |||
95 | #include "lcd-remote.h" | 95 | #include "lcd-remote.h" |
96 | #endif | 96 | #endif |
97 | 97 | ||
98 | #if CONFIG_USBOTG == USBOTG_ISP1362 | 98 | #if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362 |
99 | #include "isp1362.h" | 99 | #include "isp1362.h" |
100 | #endif | 100 | #endif |
101 | 101 | ||
102 | #if CONFIG_USBOTG == USBOTG_M5636 | 102 | #if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_M5636 |
103 | #include "m5636.h" | 103 | #include "m5636.h" |
104 | #endif | 104 | #endif |
105 | 105 | ||
@@ -350,9 +350,9 @@ static void init(void) | |||
350 | adc_init(); | 350 | adc_init(); |
351 | 351 | ||
352 | usb_init(); | 352 | usb_init(); |
353 | #if CONFIG_USBOTG == USBOTG_ISP1362 | 353 | #if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362 |
354 | isp1362_init(); | 354 | isp1362_init(); |
355 | #elif CONFIG_USBOTG == USBOTG_M5636 | 355 | #elif defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_M5636 |
356 | m5636_init(); | 356 | m5636_init(); |
357 | #endif | 357 | #endif |
358 | 358 | ||
diff --git a/firmware/target/coldfire/crt0.S b/firmware/target/coldfire/crt0.S index c177cd4e27..215ccfe432 100644 --- a/firmware/target/coldfire/crt0.S +++ b/firmware/target/coldfire/crt0.S | |||
@@ -78,7 +78,7 @@ start: | |||
78 | move.l %d0,(0x0a0,%a0) /* wait states are handled by the coldfire | 78 | move.l %d0,(0x0a0,%a0) /* wait states are handled by the coldfire |
79 | * IDE interface logic. */ | 79 | * IDE interface logic. */ |
80 | 80 | ||
81 | #if CONFIG_USBOTG == USBOTG_ISP1362 | 81 | #if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362 |
82 | /* Chip select 3 - USBOTG controller */ | 82 | /* Chip select 3 - USBOTG controller */ |
83 | move.l #0xc0000000,%d0 /* CSAR3 - Base = 0xc0000000 */ | 83 | move.l #0xc0000000,%d0 /* CSAR3 - Base = 0xc0000000 */ |
84 | move.l %d0,(0x0a4,%a0) | 84 | move.l %d0,(0x0a4,%a0) |
diff --git a/firmware/target/coldfire/iriver/system-iriver.c b/firmware/target/coldfire/iriver/system-iriver.c index 32fc44f963..1cb0a502be 100644 --- a/firmware/target/coldfire/iriver/system-iriver.c +++ b/firmware/target/coldfire/iriver/system-iriver.c | |||
@@ -85,7 +85,7 @@ void set_cpu_frequency(long frequency) | |||
85 | PLLCR = 0x018ae025 | (PLLCR & 0x70400000); | 85 | PLLCR = 0x018ae025 | (PLLCR & 0x70400000); |
86 | CSCR0 = 0x00001180; /* Flash: 4 wait states */ | 86 | CSCR0 = 0x00001180; /* Flash: 4 wait states */ |
87 | CSCR1 = 0x00001580; /* LCD: 5 wait states */ | 87 | CSCR1 = 0x00001580; /* LCD: 5 wait states */ |
88 | #if CONFIG_USBOTG == USBOTG_ISP1362 | 88 | #if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362 |
89 | CSCR3 = 0x00002180; /* USBOTG: 8 wait states */ | 89 | CSCR3 = 0x00002180; /* USBOTG: 8 wait states */ |
90 | #endif | 90 | #endif |
91 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | 91 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. |
@@ -112,7 +112,7 @@ void set_cpu_frequency(long frequency) | |||
112 | PLLCR = 0x038be025 | (PLLCR & 0x70400000); | 112 | PLLCR = 0x038be025 | (PLLCR & 0x70400000); |
113 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ | 113 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ |
114 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | 114 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ |
115 | #if CONFIG_USBOTG == USBOTG_ISP1362 | 115 | #if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362 |
116 | CSCR3 = 0x00000580; /* USBOTG: 1 wait state */ | 116 | CSCR3 = 0x00000580; /* USBOTG: 1 wait state */ |
117 | #endif | 117 | #endif |
118 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | 118 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. |
@@ -139,7 +139,7 @@ void set_cpu_frequency(long frequency) | |||
139 | PLLCR = 0x00800200 | (PLLCR & 0x70400000); | 139 | PLLCR = 0x00800200 | (PLLCR & 0x70400000); |
140 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ | 140 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ |
141 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | 141 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ |
142 | #if CONFIG_USBOTG == USBOTG_ISP1362 | 142 | #if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362 |
143 | CSCR3 = 0x00000180; /* USBOTG: 0 wait states */ | 143 | CSCR3 = 0x00000180; /* USBOTG: 0 wait states */ |
144 | #endif | 144 | #endif |
145 | DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ | 145 | DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ |