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authorMarcin Bukat <marcin.bukat@gmail.com>2023-09-27 22:32:07 +0200
committerMarcin Bukat <marcin.bukat@gmail.com>2023-09-27 22:49:38 +0200
commit0bfdb73b4d7512ca223ca44417612bcbfe2536a1 (patch)
treecd8f565d93ae6f8fcfe3d317b8d27542f01e8779
parent609db995d5ac0fb6c538c5f4e9e4e449235f7c76 (diff)
downloadrockbox-0bfdb73b4d7512ca223ca44417612bcbfe2536a1.tar.gz
rockbox-0bfdb73b4d7512ca223ca44417612bcbfe2536a1.zip
ATJ213x: Convert register description to v2 format
Diffstat
-rw-r--r--utils/regtools/desc/regs-atj213x-v1.xml1102
-rw-r--r--utils/regtools/desc/regs-atj213x.xml4811
2 files changed, 4813 insertions, 1100 deletions
diff --git a/utils/regtools/desc/regs-atj213x-v1.xml b/utils/regtools/desc/regs-atj213x-v1.xml
new file mode 100644
index 0000000000..cca7db9fc0
--- /dev/null
+++ b/utils/regtools/desc/regs-atj213x-v1.xml
@@ -0,0 +1,1102 @@
1<?xml version="1.0"?>
2<soc name="atj213x" desc="Actions atj213x">
3 <dev name="ADC" long_name="Analog to Digital Converter" desc="" version="1.0">
4 <addr name="ADC" addr="0xb0110000"/>
5 </dev>
6 <dev name="ATA" long_name="" desc="" version="1.0">
7 <addr name="ATA" addr="0xb0090000"/>
8 <reg name="CONFIG" desc="">
9 <addr name="CONFIG" addr="0x0"/>
10 </reg>
11 <reg name="UDMACTL" desc="">
12 <addr name="UDMACTL" addr="0x4"/>
13 </reg>
14 <reg name="DATA" desc="">
15 <addr name="DATA" addr="0x8"/>
16 </reg>
17 <reg name="FEATURE" desc="">
18 <addr name="FEATURE" addr="0xc"/>
19 </reg>
20 <reg name="SECCNT" desc="">
21 <addr name="SECCNT" addr="0x10"/>
22 </reg>
23 <reg name="SECNUM" desc="">
24 <addr name="SECNUM" addr="0x14"/>
25 </reg>
26 <reg name="CLDLOW" desc="">
27 <addr name="CLDL" addr="0x18"/>
28 </reg>
29 <reg name="CLDHI" desc="">
30 <addr name="CLDHIGH" addr="0x1c"/>
31 </reg>
32 <reg name="HEAD" desc="">
33 <addr name="HEAD" addr="0x20"/>
34 </reg>
35 <reg name="CMD" desc="">
36 <addr name="CMD" addr="0x24"/>
37 </reg>
38 <reg name="BYTECNT" desc="">
39 <addr name="BYTECNT" addr="0x28"/>
40 </reg>
41 <reg name="FIFOCTL" desc="">
42 <addr name="FIFOCTL" addr="0x2c"/>
43 </reg>
44 <reg name="FIFOCFG" desc="">
45 <addr name="FIFOCFG" addr="0x30"/>
46 </reg>
47 <reg name="ADDRDEC" desc="">
48 <addr name="ADDRDEC" addr="0x34"/>
49 </reg>
50 <reg name="IRQCTL" desc="">
51 <addr name="IRQCTL" addr="0x38"/>
52 </reg>
53 </dev>
54 <dev name="BOOT" long_name="" desc="" version="">
55 <addr name="BOOT" addr="0xb0038000"/>
56 <reg name="NORCTL" desc="">
57 <addr name="NORCTL" addr="0x0"/>
58 </reg>
59 <reg name="BROMCTL" desc="">
60 <addr name="BROMCTL" addr="0x4"/>
61 </reg>
62 <reg name="CHIPID" desc="">
63 <addr name="CHIPID" addr="0x8"/>
64 </reg>
65 </dev>
66 <dev name="BT" long_name="" desc="" version="">
67 <addr name="BT" addr="0xb00d0000"/>
68 </dev>
69 <dev name="CMU" long_name="Clock Management Unit" desc="" version="1.0">
70 <addr name="CMU" addr="0xb0010000"/>
71 <reg name="COREPLL" desc="">
72 <addr name="COREPLL" addr="0x0"/>
73 <field name="RESERVED31_11" desc="" bitrange="31:11"/>
74 <field name="CPBY" desc="Core PLL Bypass " bitrange="10:10"/>
75 <field name="CPBI" desc="Core PLL Bias " bitrange="9:8"/>
76 <field name="CPEN" desc="Core PLL Enable " bitrange="7:7"/>
77 <field name="HOEN" desc="High Oscillator Enable" bitrange="6:6"/>
78 <field name="CPCK" desc="COREPLLout = CPCK * 6 (MHz) (in range 12 - 378MHz)" bitrange="5:0"/>
79 </reg>
80 <reg name="DSPPLL" desc="">
81 <addr name="DSPPLL" addr="0x4"/>
82 <field name="RESERVED31_9" desc="" bitrange="31:9"/>
83 <field name="DPBI" desc="DSP PLL Bias" bitrange="8:7"/>
84 <field name="DPEN" desc="DSP PLL Enable" bitrange="6:6"/>
85 <field name="DPCK" desc="DSPPLLout = DPCK * 6 (MHz) (in range 12-378MHz)" bitrange="5:0"/>
86 </reg>
87 <reg name="AUDIOPLL" desc="">
88 <addr name="AUDIOPLL" addr="0x8"/>
89 <field name="RESERVED31_12" desc="" bitrange="31:12"/>
90 <field name="ADCPLL" desc="Audio PLL CLk Control" bitrange="11:11"/>
91 <field name="ADCCLK" desc="ADC Clock Divisor, output is FS*256" bitrange="10:8"/>
92 <field name="RESERVED7" desc="" bitrange="7:7"/>
93 <field name="APBI" desc="Audio PLL Bias" bitrange="6:5"/>
94 <field name="APEN" desc="Audio PLL Enable" bitrange="4:4"/>
95 <field name="DACPLL" desc="DAC PLL CLk Control" bitrange="3:3"/>
96 <field name="DACCLK" desc="DAC Clock Divisor, output is FS*256" bitrange="2:0"/>
97 </reg>
98 <reg name="BUSCLK" desc="Bus CLK Control Register">
99 <addr name="BUSCLK" addr="0xc"/>
100 <field name="KEYE" desc="Key Wakeup Enable" bitrange="31:31"/>
101 <field name="ALME" desc="Alarm Wakeup Enable" bitrange="30:30"/>
102 <field name="SIRE" desc="SIRQ Wakeup Enable" bitrange="29:29"/>
103 <field name="RESERVED28" desc="" bitrange="28:28"/>
104 <field name="USBE" desc="Usb Wakeup Enable" bitrange="27:27"/>
105 <field name="RESERVED26_12" desc="" bitrange="26:12"/>
106 <field name="PCLKDIV" desc="Peripheral CLK Divisor" bitrange="11:8"/>
107 <field name="CORECLKS" desc="CPU Clock Selection" bitrange="7:6"/>
108 <field name="SCLKDIV" desc="System Clock Divisor" bitrange="5:4"/>
109 <field name="CCLKDIV" desc="CPU Clock Divisor" bitrange="3:2"/>
110 <field name="DCEN" desc="Core CLK DC Enable" bitrange="1:1"/>
111 </reg>
112 <reg name="SDRCLK" desc="SDRAM Interface CLK Control Register">
113 <addr name="SDRCLK" addr="0x10"/>
114 <field name="RESERVED31_2" desc="" bitrange="31:2"/>
115 <field name="SDRDIV" desc="" bitrange="1:0"/>
116 </reg>
117 <reg name="NANDCLK" desc="NAND Interface CLK Control Register">
118 <addr name="NANDCLK" addr="0x18"/>
119 <field name="RESERVED31_4" desc="" bitrange="31:4"/>
120 <field name="NANDDIV" desc="" bitrange="3:0"/>
121 </reg>
122 <reg name="SDCLK" desc="SD Interface CLK Control Register&#10;">
123 <addr name="SDCLK" addr="0x1c"/>
124 <field name="RESERVED31_6" desc="" bitrange="31:6"/>
125 <field name="CKEN" desc="SD Interface Clock Enable" bitrange="5:5"/>
126 <field name="D128" desc="Enable Divide 128 circuit" bitrange="4:4"/>
127 <field name="SDDIV" desc="" bitrange="3:0"/>
128 </reg>
129 <reg name="MHACLK" desc="MHA CLK Control Register">
130 <addr name="MHACLK" addr="0x20"/>
131 <field name="RESERVED31_4" desc="" bitrange="31:4"/>
132 <field name="MHADIV" desc="" bitrange="3:0"/>
133 </reg>
134 <reg name="UART2CLK" desc="Uart2 CLK Control Register">
135 <addr name="UART2CLK" addr="0x2c"/>
136 <field name="RESERVED31_17" desc="" bitrange="31:17"/>
137 <field name="U2EN" desc="Uart2 Clock Enable &#10;" bitrange="16:16"/>
138 <field name="UART2DIV" desc="" bitrange="15:0"/>
139 </reg>
140 <reg name="DMACLK" desc="DMA CLK Control Register">
141 <addr name="DMACLK" addr="0x30"/>
142 <field name="RESERVED31_4" desc="" bitrange="31:4"/>
143 <field name="D7EN" desc="DMA 7 (Special Channel) Clock Enable" bitrange="3:3"/>
144 <field name="D6EN" desc="DMA 6 (Special Channel) Clock Enable" bitrange="2:2"/>
145 <field name="D5EN" desc="DMA 5 (Special Channel) Clock Enable" bitrange="1:1"/>
146 <field name="D4EN" desc="DMA 4 (Special Channel) Clock Enable" bitrange="0:0"/>
147 </reg>
148 <reg name="FMCLK" desc="FM CLK Control Register">
149 <addr name="FMCLK" addr="0x34"/>
150 <field name="RESERVED31_6" desc="" bitrange="31:6"/>
151 <field name="BCKE" desc="PWM Back Light clock Enable" bitrange="5:5"/>
152 <field name="BCKS" desc="Back Light CLK source select" bitrange="4:4"/>
153 <field name="BCKCON" desc="Divided PWM Back Light Special Clock Control" bitrange="3:2"/>
154 <field name="CLKS" desc="FM Clock Output Selection" bitrange="1:1"/>
155 <field name="OUTE" desc="FM Clock Output Enable (From Test Pin)" bitrange="0:0"/>
156 </reg>
157 <reg name="MCACLK" desc="MCA CLK Control Register">
158 <addr name="MCACLK" addr="0x38"/>
159 <field name="RESERVED31_4" desc="" bitrange="31:4"/>
160 <field name="MCADIV" desc="" bitrange="3:0"/>
161 </reg>
162 <reg name="DEVCLKEN" desc="Device CLK Control Register">
163 <addr name="DEVCLKEN" addr="0x80"/>
164 <field name="RESERVED31_27" desc="" bitrange="31:27"/>
165 <field name="GPIO" desc="" bitrange="26:26"/>
166 <field name="KEY" desc="" bitrange="25:25"/>
167 <field name="RESERVED24" desc="" bitrange="24:24"/>
168 <field name="I2C" desc="" bitrange="23:23"/>
169 <field name="UART" desc="" bitrange="22:22"/>
170 <field name="RESERVED21_19" desc="" bitrange="21:19"/>
171 <field name="ADC" desc="" bitrange="18:18"/>
172 <field name="DAC" desc="" bitrange="17:17"/>
173 <field name="DSPC" desc="" bitrange="16:16"/>
174 <field name="MCA" desc="" bitrange="15:15"/>
175 <field name="MHA" desc="" bitrange="14:14"/>
176 <field name="USBC" desc="" bitrange="13:13"/>
177 <field name="RESERVED12" desc="" bitrange="12:12"/>
178 <field name="SD" desc="" bitrange="11:11"/>
179 <field name="RESERVED10" desc="" bitrange="10:10"/>
180 <field name="NAND" desc="" bitrange="9:9"/>
181 <field name="DMAC" desc="" bitrange="8:8"/>
182 <field name="PCNT" desc="" bitrange="7:7"/>
183 <field name="SDRM" desc="" bitrange="6:6"/>
184 <field name="SDRC" desc="" bitrange="5:5"/>
185 <field name="DSPM" desc="" bitrange="4:4"/>
186 <field name="RESERVED3" desc="" bitrange="3:3"/>
187 <field name="RMOC" desc="" bitrange="2:2"/>
188 <field name="YUV" desc="" bitrange="1:1"/>
189 <field name="RESERVED0" desc="" bitrange="0:0"/>
190 </reg>
191 <reg name="DEVRST" desc="Device Reset Control Register">
192 <addr name="DEVRST" addr="0x84"/>
193 <field name="RESERVED31" desc="" bitrange="31:31"/>
194 <field name="GPIO" desc="" bitrange="30:30"/>
195 <field name="KEY" desc="" bitrange="29:29"/>
196 <field name="RESERVED28" desc="" bitrange="28:28"/>
197 <field name="I2C" desc="" bitrange="27:27"/>
198 <field name="UART" desc="" bitrange="26:26"/>
199 <field name="RESERVED25_23" desc="" bitrange="25:23"/>
200 <field name="ADC" desc="" bitrange="22:22"/>
201 <field name="DAC" desc="" bitrange="21:21"/>
202 <field name="DSPC" desc="DSP control block reset" bitrange="20:20"/>
203 <field name="INTC" desc="" bitrange="19:19"/>
204 <field name="RTC" desc="" bitrange="18:18"/>
205 <field name="PMU" desc="" bitrange="17:17"/>
206 <field name="RESERVED16_14" desc="" bitrange="16:14"/>
207 <field name="DSPM" desc="SRAM DSP MEM reset" bitrange="13:13"/>
208 <field name="TVENC" desc="" bitrange="12:12"/>
209 <field name="YUV" desc="" bitrange="11:11"/>
210 <field name="MCA" desc="" bitrange="10:10"/>
211 <field name="USB" desc="" bitrange="9:9"/>
212 <field name="RESERVED8" desc="" bitrange="8:8"/>
213 <field name="MHA" desc="" bitrange="7:7"/>
214 <field name="SD" desc="" bitrange="6:6"/>
215 <field name="NAND" desc="" bitrange="5:5"/>
216 <field name="RESERVED4" desc="" bitrange="4:4"/>
217 <field name="DMAC" desc="" bitrange="3:3"/>
218 <field name="PCNT" desc="" bitrange="2:2"/>
219 <field name="RESERVED1" desc="" bitrange="1:1"/>
220 <field name="SDR" desc="SDRAM Control register and SDRAM block Reset" bitrange="0:0"/>
221 </reg>
222 </dev>
223 <dev name="DAC" long_name="Digital Analog Converter" desc="" version="1.0">
224 <addr name="DAC" addr="0xb0100000"/>
225 </dev>
226 <dev name="DMAC" long_name="Direct Memory Access Controller" desc="Channels 0-3 work with retular AHB bus, channels 4-7 work with 'special' bus." version="">
227 <addr name="DMAC" addr="0xb0060000"/>
228 <reg name="CTL" desc="">
229 <addr name="CTL" addr="0x0"/>
230 </reg>
231 <reg name="IRQEN" desc="">
232 <addr name="IRQEN" addr="0x4"/>
233 </reg>
234 <reg name="IRQPD" desc="">
235 <addr name="IRQPD" addr="0x8"/>
236 </reg>
237 <reg name="DMA_MODE" desc="">
238 <formula string="0x100+n*0x20"/>
239 <addr name="DMA_MODE0" addr="0x100"/>
240 <addr name="DMA_MODE1" addr="0x120"/>
241 <addr name="DMA_MODE2" addr="0x140"/>
242 <addr name="DMA_MODE3" addr="0x160"/>
243 <addr name="DMA_MODE4" addr="0x180"/>
244 <addr name="DMA_MODE5" addr="0x1a0"/>
245 <addr name="DMA_MODE6" addr="0x1c0"/>
246 <addr name="DMA_MODE7" addr="0x1e0"/>
247 <field name="DBURLEN" desc="Destination burst length. If burst lenght is 4 or 8 DDIR must be 0, DFXA must be 0, DDSP must be 0, DCOL must be 0. Burst must not cross a 1kB address boundary." bitrange="31:29">
248 <value name="SINGLE" value="0x0" desc=""/>
249 <value name="INCR4" value="0x3" desc=""/>
250 <value name="INCR8" value="0x5" desc=""/>
251 </field>
252 <field name="RELO" desc="DMA Reload Bit." bitrange="28:28"/>
253 <field name="DDSP" desc="Destination DSP mode.&#10;" bitrange="27:27"/>
254 <field name="DCOL" desc="Destination Column Mode." bitrange="26:26"/>
255 <field name="DDIR" desc="Destination address direction. If DBURLEN is INCR4 or INCR8 only INCREASE is allowed." bitrange="25:25">
256 <value name="INCREASE" value="0x0" desc=""/>
257 <value name="DECREASE" value="0x1" desc=""/>
258 </field>
259 <field name="DFXA" desc="Destination Fixed Address bit." bitrange="24:24">
260 <value name="NOT_FIXED" value="0x0" desc=""/>
261 <value name="FIXED" value="0x1" desc=""/>
262 </field>
263 <field name="DTRG" desc="Destination DRQ Trig Source." bitrange="23:19">
264 <value name="DAC" value="0x6" desc=""/>
265 <value name="SDRAM" value="0x10" desc=""/>
266 <value name="IRAM" value="0x11" desc=""/>
267 <value name="SD" value="0x16" desc=""/>
268 <value name="OTG" value="0x17" desc=""/>
269 <value name="LCM" value="0x18" desc=""/>
270 </field>
271 <field name="DTRANWID" desc="" bitrange="18:17">
272 <value name="WIDTH8" value="0x0" desc=""/>
273 <value name="WIDTH16" value="0x1" desc=""/>
274 <value name="WIDTH32" value="0x2" desc=""/>
275 </field>
276 <field name="DFXS" desc="If DFXS=0, DMA will transfer in 8bit mode when remain counter is less than DTRANWID. &#10;If DFXS=1, DMA will always transfer in DTRANWID. &#10;" bitrange="16:16"/>
277 <field name="SBURLEN" desc="Source burst length. If burst lenght is 4 or 8 DDIR must be 0, DFXA must be 0, DDSP must be 0, DCOL must be 0. Burst must not cross a 1kB address boundary." bitrange="15:13">
278 <value name="SINGLE" value="0x0" desc=""/>
279 <value name="INCR4" value="0x3" desc=""/>
280 <value name="INCR8" value="0x5" desc=""/>
281 </field>
282 <field name="SDSP" desc="Source DSP mode. &#10;" bitrange="11:11"/>
283 <field name="SCOL" desc="Source Column Mode." bitrange="10:10"/>
284 <field name="SDIR" desc="Source address direction. If SBURLEN is INCR4 or INCR8 only INCREASE is allowed." bitrange="9:9">
285 <value name="INCREASE" value="0x0" desc=""/>
286 <value name="DECREASE" value="0x1" desc=""/>
287 </field>
288 <field name="SFXA" desc="Source Fixed Addres bit." bitrange="8:8">
289 <value name="NOT_FIXED" value="0x0" desc=""/>
290 <value name="FIXED" value="0x1" desc=""/>
291 </field>
292 <field name="STRG" desc="DRQ trig source." bitrange="7:3">
293 <value name="DAC" value="0x6" desc=""/>
294 <value name="SDRAM" value="0x10" desc=""/>
295 <value name="IRAM" value="0x11" desc=""/>
296 <value name="SD" value="0x16" desc=""/>
297 <value name="OTG" value="0x17" desc=""/>
298 <value name="LCM" value="0x18" desc=""/>
299 </field>
300 <field name="STRANWID" desc="" bitrange="2:1">
301 <value name="WIDTH8" value="0x0" desc=""/>
302 <value name="WIDTH16" value="0x1" desc=""/>
303 <value name="WIDTH32" value="0x2" desc=""/>
304 </field>
305 <field name="SFXS" desc="Source Fix Size. If DFXS=0, DMA will transfer in 8bit mode when remain counter is less than STRANWID. If SFXS=1, DMA will always transfer in STRANWID." bitrange="0:0"/>
306 </reg>
307 <reg name="DMA_SRC" desc="">
308 <formula string="0x104+n*0x20"/>
309 <addr name="DMA_SRC0" addr="0x104"/>
310 <addr name="DMA_SRC1" addr="0x124"/>
311 <addr name="DMA_SRC2" addr="0x144"/>
312 <addr name="DMA_SRC3" addr="0x164"/>
313 <addr name="DMA_SRC4" addr="0x184"/>
314 <addr name="DMA_SRC5" addr="0x1a4"/>
315 <addr name="DMA_SRC6" addr="0x1c4"/>
316 <addr name="DMA_SRC7" addr="0x1e4"/>
317 </reg>
318 <reg name="DMA_DST" desc="">
319 <formula string="0x108+n*0x20"/>
320 <addr name="DMA_DST0" addr="0x108"/>
321 <addr name="DMA_DST1" addr="0x128"/>
322 <addr name="DMA_DST2" addr="0x148"/>
323 <addr name="DMA_DST3" addr="0x168"/>
324 <addr name="DMA_DST4" addr="0x188"/>
325 <addr name="DMA_DST5" addr="0x1a8"/>
326 <addr name="DMA_DST6" addr="0x1c8"/>
327 <addr name="DMA_DST7" addr="0x1e8"/>
328 </reg>
329 <reg name="DMA_CNT" desc="">
330 <formula string="0x10c+n*0x20"/>
331 <addr name="DMA_CNT0" addr="0x10c"/>
332 <addr name="DMA_CNT1" addr="0x12c"/>
333 <addr name="DMA_CNT2" addr="0x14c"/>
334 <addr name="DMA_CNT3" addr="0x16c"/>
335 <addr name="DMA_CNT4" addr="0x18c"/>
336 <addr name="DMA_CNT5" addr="0x1ac"/>
337 <addr name="DMA_CNT6" addr="0x1cc"/>
338 <addr name="DMA_CNT7" addr="0x1ec"/>
339 </reg>
340 <reg name="DMA_REM" desc="">
341 <formula string="0x110+n*0x20"/>
342 <addr name="DMA_REM0" addr="0x110"/>
343 <addr name="DMA_REM1" addr="0x130"/>
344 <addr name="DMA_REM2" addr="0x150"/>
345 <addr name="DMA_REM3" addr="0x170"/>
346 <addr name="DMA_REM4" addr="0x190"/>
347 <addr name="DMA_REM5" addr="0x1b0"/>
348 <addr name="DMA_REM6" addr="0x1d0"/>
349 <addr name="DMA_REM7" addr="0x1f0"/>
350 </reg>
351 <reg name="DMA_CMD" desc="">
352 <formula string="0x114+n*0x20"/>
353 <addr name="DMA_CMD0" addr="0x114"/>
354 <addr name="DMA_CMD1" addr="0x134"/>
355 <addr name="DMA_CMD2" addr="0x154"/>
356 <addr name="DMA_CMD3" addr="0x174"/>
357 <addr name="DMA_CMD4" addr="0x194"/>
358 <addr name="DMA_CMD5" addr="0x1b4"/>
359 <addr name="DMA_CMD6" addr="0x1d4"/>
360 <addr name="DMA_CMD7" addr="0x1f4"/>
361 </reg>
362 </dev>
363 <dev name="DSP" long_name="Digital Signal Processor" desc="" version="1.0">
364 <addr name="DSP" addr="0xb0050000"/>
365 <reg name="HDR" desc="HIP data registers">
366 <addr name="HDR0" addr="0x0"/>
367 <addr name="HDR1" addr="0x4"/>
368 <addr name="HDR2" addr="0x8"/>
369 <addr name="HDR3" addr="0xc"/>
370 <addr name="HDR4" addr="0x10"/>
371 <addr name="HDR5" addr="0x14"/>
372 <addr name="HSR6" addr="0x18"/>
373 <addr name="HSR7" addr="0x1c"/>
374 </reg>
375 <reg name="CTL" desc="">
376 <addr name="CTL" addr="0x20"/>
377 </reg>
378 </dev>
379 <dev name="GPIO" long_name="" desc="" version="1.0">
380 <addr name="GPIO" addr="0xb01c0000"/>
381 <reg name="OUTEN" desc="">
382 <addr name="AOUTEN" addr="0x0"/>
383 <addr name="BOUTEN" addr="0xc"/>
384 </reg>
385 <reg name="INEN" desc="">
386 <addr name="AINEN" addr="0x4"/>
387 <addr name="BINEN" addr="0x10"/>
388 </reg>
389 <reg name="DAT" desc="">
390 <addr name="ADAT" addr="0x8"/>
391 <addr name="BDAT" addr="0x14"/>
392 </reg>
393 <reg name="MFCTL0" desc="">
394 <addr name="MFCTL0" addr="0x18"/>
395 <field name="RESERVED31_25" desc="" bitrange="31:25"/>
396 <field name="GPIOA2_0" desc="" bitrange="24:22">
397 <value name="NAND_CLE_RB_ALE" value="0x1" desc=""/>
398 <value name="LCD_RS_WD9_WD0" value="0x2" desc=""/>
399 <value name="SD_CMD" value="0x4" desc=""/>
400 </field>
401 <field name="CEB6" desc="" bitrange="21:20">
402 <value name="LCD_CE" value="0x2" desc=""/>
403 <value name="SD_CLK" value="0x3" desc=""/>
404 </field>
405 <field name="RESERVED19_16" desc="" bitrange="19:16"/>
406 <field name="CEB3" desc="" bitrange="15:14">
407 <value name="NAND_CEB3" value="0x1" desc=""/>
408 <value name="LCD_CE" value="0x2" desc=""/>
409 </field>
410 <field name="CEB2" desc="" bitrange="13:12">
411 <value name="NAND_CEB2" value="0x1" desc=""/>
412 <value name="LCD_CE" value="0x2" desc=""/>
413 </field>
414 <field name="CEB1" desc="" bitrange="11:10">
415 <value name="NAND_CEB1" value="0x1" desc=""/>
416 <value name="LCD_CE" value="0x2" desc=""/>
417 </field>
418 <field name="CEB0" desc="" bitrange="9:8">
419 <value name="NAND_CEB0" value="0x1" desc=""/>
420 <value name="LCD_CE" value="0x2" desc=""/>
421 </field>
422 <field name="WRRD" desc="" bitrange="7:6">
423 <value name="NAND_WR_RD" value="0x1" desc=""/>
424 <value name="LCD_WRB_RDB" value="0x2" desc=""/>
425 </field>
426 <field name="NAND_D7_0" desc="" bitrange="5:3">
427 <value name="NAND_D7_0" value="0x1" desc=""/>
428 <value name="LCD_WD17_10" value="0x2" desc=""/>
429 </field>
430 <field name="NAND_D15_8" desc="" bitrange="2:0">
431 <value name="NAND_D15_8" value="0x1" desc=""/>
432 <value name="LCD_WD8_1" value="0x2" desc=""/>
433 <value name="SDR_D7_0" value="0x4" desc=""/>
434 </field>
435 </reg>
436 <reg name="MFCTL1" desc="">
437 <addr name="MFCTL1" addr="0x1c"/>
438 <field name="MFEN" desc="" bitrange="31:31"/>
439 <field name="RESERVED30_18" desc="" bitrange="30:18"/>
440 <field name="SD2E" desc="" bitrange="17:17"/>
441 <field name="RBS" desc="" bitrange="16:16"/>
442 <field name="RESERVED15_12" desc="" bitrange="15:12"/>
443 <field name="SIR0" desc="" bitrange="11:11"/>
444 <field name="SPTR" desc="" bitrange="10:9">
445 <value name="I2C1_SCL_ADA" value="0x1" desc=""/>
446 <value name="UART2_TX_RX" value="0x2" desc=""/>
447 </field>
448 <field name="U2TR" desc="" bitrange="8:8">
449 <value name="UART2_TX_RX" value="0x0" desc=""/>
450 <value name="I2C2_SCL_SDA" value="0x1" desc=""/>
451 </field>
452 <field name="RESERVED7_6" desc="" bitrange="7:6"/>
453 <field name="I2C1SS" desc="" bitrange="5:4">
454 <value name="I2C1_SCL_SDA" value="0x0" desc=""/>
455 <value name="UART2_TX_RX" value="0x1" desc=""/>
456 </field>
457 <field name="RESERVED3_0" desc="" bitrange="3:0"/>
458 </reg>
459 </dev>
460 <dev name="I2C" long_name="" desc="" version="1.0">
461 <addr name="I2C1" addr="0xb0180000"/>
462 <addr name="I2C2" addr="0xb0180020"/>
463 <reg name="CTL" desc="">
464 <addr name="CTL" addr="0x0"/>
465 <field name="RESERVED31_9" desc="" bitrange="31:9"/>
466 <field name="PUEN" desc="nternal Pull-up Resistor (4.7k) Enable" bitrange="8:8"/>
467 <field name="EN" desc="Block enable" bitrange="7:7"/>
468 <field name="SIE" desc="START Condition Generates IRQ Enable (only for slave mode)" bitrange="6:6"/>
469 <field name="IRQE" desc="IRQ Enable" bitrange="5:5"/>
470 <field name="MS" desc="Mode select" bitrange="4:4">
471 <value name="MASTER" value="0x0" desc=""/>
472 <value name="SLAVE" value="0x1" desc=""/>
473 </field>
474 <field name="GBCC" desc="Generating Bus Control Condition (only for master mode)" bitrange="3:2">
475 <value name="NOP" value="0x0" desc=""/>
476 <value name="START" value="0x1" desc=""/>
477 <value name="STOP" value="0x2" desc=""/>
478 <value name="REPEATED_START" value="0x3" desc=""/>
479 </field>
480 <field name="RB" desc="Release Bus. Writing 1 to this bit will release the clock and data line to idle. MCU should write 1 to this bit after transmitting or receiving the last bit of&#10;the whole transfer.&#10;" bitrange="1:1"/>
481 <field name="GRAS" desc="Generating/Receiving Acknowledge Signal" bitrange="0:0"/>
482 </reg>
483 <reg name="CLKDIV" desc="">
484 <addr name="CLKDIV" addr="0x4"/>
485 <field name="RESERVED31_8" desc="" bitrange="31:8"/>
486 <field name="CLKDIV" desc="Clock Divider Factor (only for master mode). I2Cx clock (SCL) can select standard (100kbps) mode and fast (400kbps) mode. Calculating SCL is as follows: SCL=PCLK/(CLKDIV*16)&#10;" bitrange="7:0"/>
487 </reg>
488 <reg name="STAT" desc="">
489 <addr name="STAT" addr="0x8"/>
490 <field name="RESERVED31_8" desc="" bitrange="31:8"/>
491 <field name="TRC" desc="Transmit/Receive Complete Bit" bitrange="7:7"/>
492 <field name="STPD" desc="STOP Detect Bit " bitrange="6:6"/>
493 <field name="STAD" desc="START Detect Bit" bitrange="5:5"/>
494 <field name="RWST" desc="Read/Write Status Bit (only for Slave mode)" bitrange="4:4"/>
495 <field name="LBST" desc="Last Byte Status Bit" bitrange="3:3"/>
496 <field name="IRQP" desc="IRQ Pending Bit" bitrange="2:2"/>
497 <field name="OVST" desc="Overflow Status Bit" bitrange="1:1"/>
498 <field name="WCO" desc="Writing Collision Bit" bitrange="0:0"/>
499 </reg>
500 <reg name="ADDR" desc="">
501 <addr name="ADDR" addr="0xc"/>
502 <field name="RESERVED31_8" desc="" bitrange="31:8"/>
503 <field name="SDAD" desc="Slave Device Address" bitrange="7:1"/>
504 <field name="RWCM" desc="Read/Write Control or Match" bitrange="0:0"/>
505 </reg>
506 <reg name="DAT" desc="">
507 <addr name="DAT" addr="0x10"/>
508 <field name="RESERVED31_8" desc="" bitrange="31:8"/>
509 <field name="TXRXDAT" desc="Transmit/Receive Data" bitrange="7:0"/>
510 </reg>
511 </dev>
512 <dev name="INTC" long_name="Interrupt Controller" desc="" version="1.0">
513 <addr name="INTC" addr="0xb0020000"/>
514 <reg name="PD" desc="">
515 <addr name="PD" addr="0x0"/>
516 </reg>
517 <reg name="MSK" desc="">
518 <addr name="MSK" addr="0x4"/>
519 </reg>
520 <reg name="CFG" desc="">
521 <addr name="CFG0" addr="0x8"/>
522 <addr name="CFG1" addr="0xc"/>
523 <addr name="CFG2" addr="0x10"/>
524 </reg>
525 <reg name="EXTCTL" desc="">
526 <addr name="EXTCTL" addr="0x14"/>
527 </reg>
528 </dev>
529 <dev name="IR" long_name="" desc="" version="1.0">
530 <addr name="IR" addr="0xb0160010"/>
531 </dev>
532 <dev name="KEY" long_name="" desc="" version="1.0">
533 <addr name="KEY" addr="0xb01a0000"/>
534 </dev>
535 <dev name="MCA" long_name="Motion Compensation Accelerator" desc="" version="1.0">
536 <addr name="MCA" addr="0xb0080000"/>
537 <reg name="CTL" desc="">
538 <addr name="CTL" addr="0x0"/>
539 </reg>
540 </dev>
541 <dev name="MHA" long_name="Media Hardware Accelerator" desc="" version="1.0">
542 <addr name="MHA" addr="0xb00c0000"/>
543 <reg name="CTL" desc="">
544 <addr name="CTL" addr="0x0"/>
545 </reg>
546 <reg name="CFG" desc="">
547 <addr name="CFG" addr="0x4"/>
548 </reg>
549 <reg name="DCSCLx" desc="">
550 <addr name="DCSCL0" addr="0x10"/>
551 <addr name="DCSCL1" addr="0x14"/>
552 <addr name="DCSCL2" addr="0x18"/>
553 <addr name="DCSCL3" addr="0x1c"/>
554 </reg>
555 <reg name="QSCL" desc="">
556 <addr name="QSCL" addr="0x20"/>
557 </reg>
558 </dev>
559 <dev name="NAND" long_name="NAND Flash Interface" desc="" version="1.0">
560 <addr name="NAND" addr="0xb00a0000"/>
561 <reg name="CTL" desc="">
562 <addr name="CTL" addr="0x0"/>
563 </reg>
564 <reg name="STATUS" desc="">
565 <addr name="STATUS" addr="0x4"/>
566 </reg>
567 <reg name="FIFOTIM" desc="">
568 <addr name="FIFOTIM" addr="0x8"/>
569 </reg>
570 <reg name="CLKCTL" desc="">
571 <addr name="CLKCTL" addr="0xc"/>
572 </reg>
573 <reg name="BYTECNT" desc="">
574 <addr name="BYTECNT" addr="0x10"/>
575 </reg>
576 <reg name="ADDR01" desc="">
577 <addr name="ADDR01" addr="0x14"/>
578 </reg>
579 <reg name="ADDR23" desc="">
580 <addr name="ADDR23" addr="0x18"/>
581 </reg>
582 <reg name="ADDR45" desc="">
583 <addr name="ADDR45" addr="0x1c"/>
584 </reg>
585 <reg name="ADDR67" desc="">
586 <addr name="ADDR67" addr="0x20"/>
587 </reg>
588 <reg name="BUF" desc="">
589 <addr name="BUF0" addr="0x24"/>
590 <addr name="BUF1" addr="0x28"/>
591 </reg>
592 <reg name="CMD" desc="">
593 <addr name="CMD" addr="0x2c"/>
594 </reg>
595 <reg name="ECCCTL" desc="">
596 <addr name="ECCCTL" addr="0x30"/>
597 </reg>
598 <reg name="HAMECC" desc="">
599 <addr name="HAMECC0" addr="0x34"/>
600 <addr name="HAMECC1" addr="0x38"/>
601 <addr name="HAMECC2" addr="0x3c"/>
602 </reg>
603 <reg name="HAMCEC" desc="">
604 <addr name="HAMCEC" addr="0x40"/>
605 </reg>
606 <reg name="RSE" desc="">
607 <addr name="RSE0" addr="0x44"/>
608 <addr name="RSE1" addr="0x48"/>
609 <addr name="RSE2" addr="0x4c"/>
610 <addr name="RSE3" addr="0x50"/>
611 </reg>
612 <reg name="RSPS" desc="">
613 <addr name="RSPS0" addr="0x54"/>
614 <addr name="RSPS1" addr="0x58"/>
615 <addr name="RSPS2" addr="0x5c"/>
616 </reg>
617 <reg name="FIFODATA" desc="">
618 <addr name="FIFODATA" addr="0x60"/>
619 </reg>
620 <reg name="DEBUG" desc="">
621 <addr name="DEBUG" addr="0x70"/>
622 </reg>
623 </dev>
624 <dev name="PCM" long_name="" desc="" version="1.0">
625 <addr name="PCM" addr="0xb0150000"/>
626 </dev>
627 <dev name="PCNT" long_name="Performance Counters" desc="The base address is not clear!" version="1.0">
628 <addr name="PCNT" addr="0xb003c000"/>
629 <reg name="CTL" desc="">
630 <addr name="CTL" addr="0x0"/>
631 </reg>
632 <reg name="PCx" desc="">
633 <addr name="PC0" addr="0x4"/>
634 <addr name="PC1" addr="0x8"/>
635 </reg>
636 </dev>
637 <dev name="PMU" long_name="Power Management Unit" desc="" version="1.0">
638 <addr name="PMU" addr="0xb0000000"/>
639 <reg name="CTL" desc="">
640 <addr name="CTL" addr="0x0"/>
641 <field name="LBRM" desc="" bitrange="31:31"/>
642 <field name="VCVS" desc="" bitrange="30:28"/>
643 <field name="LBNM" desc="" bitrange="27:27"/>
644 <field name="VDVS" desc="" bitrange="26:24"/>
645 <field name="VCDE" desc="" bitrange="23:23"/>
646 <field name="VCVD" desc="" bitrange="22:20"/>
647 <field name="VDDE" desc="" bitrange="19:19"/>
648 <field name="VDVD" desc="" bitrange="18:16"/>
649 <field name="BLEN" desc="" bitrange="15:15"/>
650 <field name="VCOE" desc="" bitrange="14:14"/>
651 <field name="LA6E" desc="" bitrange="13:13"/>
652 <field name="LA4E" desc="" bitrange="12:12"/>
653 <field name="IBIAS" desc="" bitrange="11:10"/>
654 <field name="OSCFREQ" desc="" bitrange="9:8"/>
655 <field name="DC1M" desc="" bitrange="7:7"/>
656 <field name="DC2M" desc="" bitrange="6:6"/>
657 <field name="BLVS" desc="" bitrange="5:3"/>
658 <field name="VDV0" desc="" bitrange="2:2"/>
659 <field name="PWRM" desc="" bitrange="1:0"/>
660 </reg>
661 <reg name="LRADC" desc="">
662 <addr name="LRADC" addr="0x4"/>
663 <field name="RESERVED31_28" desc="" bitrange="31:28"/>
664 <field name="REMOADC4" desc="" bitrange="27:24"/>
665 <field name="RESERVED23_20" desc="" bitrange="23:22"/>
666 <field name="BATADC6" desc="" bitrange="21:16"/>
667 <field name="RESERVED15_14" desc="" bitrange="15:14"/>
668 <field name="TEMPADC6" desc="" bitrange="13:8"/>
669 <field name="RESERVED7_0" desc="" bitrange="7:0"/>
670 </reg>
671 <reg name="CHG" desc="">
672 <addr name="CHG" addr="0x8"/>
673 <field name="EN" desc="" bitrange="31:31"/>
674 <field name="CURRENT" desc="" bitrange="30:28">
675 <value name="CURRENT_50mA" value="0x0" desc=""/>
676 <value name="CURRENT_100mA" value="0x1" desc=""/>
677 <value name="CURRENT_150mA" value="0x2" desc=""/>
678 <value name="CURRENT_200mA" value="0x3" desc=""/>
679 <value name="CURRENT_250mA" value="0x4" desc=""/>
680 <value name="CURRENT_300mA" value="0x5" desc=""/>
681 <value name="CURRENT_400mA" value="0x6" desc=""/>
682 <value name="CURRENT_500mA" value="0x7" desc=""/>
683 </field>
684 <field name="STAT" desc="" bitrange="27:27">
685 <value name="DISCHARGING" value="0x0" desc=""/>
686 <value name="CHARGING" value="0x1" desc=""/>
687 </field>
688 <field name="CHGPHASE" desc="" bitrange="26:25">
689 <value name="RESERVED" value="0x0" desc=""/>
690 <value name="PRECHARGE" value="0x1" desc=""/>
691 <value name="CC" value="0x2" desc=""/>
692 <value name="CV" value="0x3" desc=""/>
693 </field>
694 <field name="RESERVED24_16" desc="" bitrange="24:16"/>
695 <field name="PBLS" desc="" bitrange="15:15"/>
696 <field name="PPHS" desc="" bitrange="14:14"/>
697 <field name="RESERVED13" desc="" bitrange="13:13"/>
698 <field name="PDUT" desc="" bitrange="12:8"/>
699 <field name="RESERVED7" desc="" bitrange="7:7"/>
700 <field name="BLV0" desc="" bitrange="6:6"/>
701 <field name="TMPSET" desc="" bitrange="5:4">
702 <value name="TEMP_40C" value="0x0" desc=""/>
703 <value name="TEMP_45C" value="0x1" desc=""/>
704 <value name="TEMP_50C" value="0x2" desc=""/>
705 <value name="TEMP_55C" value="0x3" desc=""/>
706 </field>
707 <field name="LBNMIVS" desc="" bitrange="3:2">
708 <value name="VOLTAGE_2_9" value="0x0" desc=""/>
709 <value name="VOLTAGE_3_1" value="0x1" desc=""/>
710 <value name="VOLTAGE_3_3" value="0x2" desc=""/>
711 <value name="VOLTAGE_3_5" value="0x3" desc=""/>
712 </field>
713 <field name="LBRVS" desc="" bitrange="1:0">
714 <value name="VOLTAGE_2_7" value="0x0" desc=""/>
715 <value name="VOLTAGE_2_9" value="0x1" desc=""/>
716 <value name="VOLTAGE_3_1" value="0x2" desc=""/>
717 <value name="VOLTAGE_3_3" value="0x3" desc=""/>
718 </field>
719 </reg>
720 </dev>
721 <dev name="RTCWDT" long_name="Real Time Clock, Timers and Watchdog" desc="" version="1.0">
722 <addr name="RTC" addr="0xb0018000"/>
723 <reg name="CTL" desc="">
724 <addr name="CTL" addr="0x0"/>
725 </reg>
726 <reg name="DHMS" desc="">
727 <addr name="DHMS" addr="0x4"/>
728 <field name="RESERVED31_27" desc="" bitrange="31:27"/>
729 <field name="DAY" desc="" bitrange="26:24"/>
730 <field name="RESERVED23_21" desc="" bitrange="23:21"/>
731 <field name="HOUR" desc="" bitrange="20:16"/>
732 <field name="RESERVED15_14" desc="" bitrange="15:14"/>
733 <field name="MIN" desc="" bitrange="13:8"/>
734 <field name="RESERVED7_6" desc="" bitrange="7:6"/>
735 <field name="SEC" desc="" bitrange="5:0"/>
736 </reg>
737 <reg name="YMD" desc="">
738 <addr name="YMD" addr="0x8"/>
739 <field name="RESERVED31" desc="" bitrange="31:31"/>
740 <field name="CENT" desc="" bitrange="30:24"/>
741 <field name="RESERVED23" desc="" bitrange="23:23"/>
742 <field name="YEAR" desc="" bitrange="22:16"/>
743 <field name="RESERVED15_12" desc="" bitrange="15:12"/>
744 <field name="MON" desc="" bitrange="11:8"/>
745 <field name="RESERVED7_5" desc="" bitrange="7:5"/>
746 <field name="DATE" desc="" bitrange="4:0"/>
747 </reg>
748 <reg name="DHMSALM" desc="">
749 <addr name="DHMSALM" addr="0xc"/>
750 <field name="RESERVED31_21" desc="" bitrange="31:21"/>
751 <field name="HOURAL" desc="" bitrange="20:16"/>
752 <field name="RESERVED15_14" desc="" bitrange="15:14"/>
753 <field name="MINAL" desc="" bitrange="13:8"/>
754 <field name="RESERVED7_6" desc="" bitrange="7:6"/>
755 <field name="SECAL" desc="" bitrange="5:0"/>
756 </reg>
757 <reg name="YMDALM" desc="">
758 <addr name="YMDALM" addr="0x10"/>
759 <field name="RESERVED31_23" desc="" bitrange="31:23"/>
760 <field name="YEARAL" desc="" bitrange="22:16"/>
761 <field name="RESERVED15_12" desc="" bitrange="15:12"/>
762 <field name="MONAL" desc="" bitrange="11:8"/>
763 <field name="RESERVED7_5" desc="" bitrange="7:5"/>
764 <field name="DATEAL" desc="" bitrange="4:0"/>
765 </reg>
766 <reg name="WDCTL" desc="">
767 <addr name="WDCTL" addr="0x14"/>
768 </reg>
769 <reg name="TxCTL" desc="">
770 <addr name="T0CTL" addr="0x18"/>
771 <addr name="T1CTL" addr="0x20"/>
772 </reg>
773 <reg name="Tx" desc="">
774 <addr name="T0" addr="0x1c"/>
775 <addr name="T1" addr="0x24"/>
776 </reg>
777 </dev>
778 <dev name="SD" long_name="SD/MMC Interface" desc="" version="">
779 <addr name="SD" addr="0xb00b0000"/>
780 <reg name="CTL" desc="">
781 <addr name="CTL" addr="0x0"/>
782 </reg>
783 <reg name="CMDRSP" desc="">
784 <addr name="CMDRSP" addr="0x4"/>
785 </reg>
786 <reg name="RW" desc="">
787 <addr name="RW" addr="0x8"/>
788 </reg>
789 <reg name="FIFOCTL" desc="">
790 <addr name="FIFOCTL" addr="0xc"/>
791 </reg>
792 <reg name="CMD" desc="">
793 <addr name="CMD" addr="0x10"/>
794 </reg>
795 <reg name="ARG" desc="">
796 <addr name="ARG" addr="0x14"/>
797 </reg>
798 <reg name="CRC7" desc="">
799 <addr name="CRC7" addr="0x18"/>
800 </reg>
801 <reg name="RSPBUFx" desc="">
802 <addr name="RSPBUF0" addr="0x1c"/>
803 <addr name="RSPBUF1" addr="0x20"/>
804 <addr name="RSPBUF2" addr="0x24"/>
805 <addr name="RSPBUF3" addr="0x28"/>
806 <addr name="RSPBUF4" addr="0x2c"/>
807 </reg>
808 <reg name="DAT" desc="">
809 <addr name="DAT" addr="0x30"/>
810 </reg>
811 <reg name="CLK" desc="">
812 <addr name="CLK" addr="0x34"/>
813 </reg>
814 <reg name="BYTECNT" desc="">
815 <addr name="BYTECNT" addr="0x38"/>
816 </reg>
817 </dev>
818 <dev name="SDR" long_name="SDRAM Interface" desc="" version="1.0">
819 <addr name="SDR" addr="0xb0070000"/>
820 <reg name="CTL" desc="">
821 <addr name="CTL" addr="0x0"/>
822 </reg>
823 <reg name="ADDRCFG" desc="">
824 <addr name="ADDRCFG" addr="0x4"/>
825 </reg>
826 <reg name="EN" desc="">
827 <addr name="EN" addr="0x8"/>
828 <field name="RESERVED31_1" desc="" bitrange="31:1"/>
829 <field name="EN" desc="" bitrange="0:0"/>
830 </reg>
831 <reg name="CMD" desc="">
832 <addr name="CMD" addr="0xc"/>
833 </reg>
834 <reg name="STAT" desc="">
835 <addr name="STAT" addr="0x10"/>
836 </reg>
837 <reg name="RFSH" desc="">
838 <addr name="RFSH" addr="0x14"/>
839 </reg>
840 <reg name="MODE" desc="">
841 <addr name="MODE" addr="0x18"/>
842 </reg>
843 <reg name="MOBILE" desc="">
844 <addr name="MOBILE" addr="0x1c"/>
845 </reg>
846 </dev>
847 <dev name="SPDIF" long_name="Sony Philips Digital Interface" desc="" version="1.0">
848 <addr name="SPDIF" addr="0xb0140000"/>
849 </dev>
850 <dev name="SPI" long_name="" desc="" version="1.0">
851 <addr name="SPI" addr="0xb0190000"/>
852 </dev>
853 <dev name="SRAMOC" long_name="SRAM on Chip" desc="" version="1.0">
854 <addr name="SRAMOC" addr="0xb0030000"/>
855 <reg name="CTL" desc="">
856 <addr name="CTL" addr="0x0"/>
857 </reg>
858 <reg name="STAT" desc="">
859 <addr name="STAT" addr="0x4"/>
860 </reg>
861 </dev>
862 <dev name="TP" long_name="" desc="" version="1.0">
863 <addr name="TP" addr="0xb0120000"/>
864 </dev>
865 <dev name="UART" long_name="" desc="" version="1.0">
866 <addr name="UART0" addr="0xb0160000"/>
867 <addr name="UART1" addr="0xb0160020"/>
868 </dev>
869 <dev name="UDC" long_name="Usb Device Controller" desc="CAST cusb2-otg IP core" version="1.0">
870 <addr name="UDC" addr="0xb00e0000"/>
871 <reg name="EP0BC" desc="ep0 byte count register">
872 <addr name="OUT0BC" addr="0x0"/>
873 <addr name="IN0BC" addr="0x1"/>
874 <field name="RESERVED" desc="" bitrange="31:8"/>
875 <field name="BC" desc="" bitrange="7:0"/>
876 </reg>
877 <reg name="EP0CS" desc="">
878 <addr name="EP0CS" addr="0x2"/>
879 <field name="RESERVED" desc="" bitrange="31:8"/>
880 <field name="OUT_BUSY" desc="" bitrange="3:3"/>
881 <field name="IN_BUSY" desc="" bitrange="2:2"/>
882 <field name="NAK" desc="Writing 1 clears" bitrange="1:1"/>
883 <field name="STALL" desc="" bitrange="0:0"/>
884 </reg>
885 <reg name="BCL" desc="Endpoint byte count LSB register">
886 <addr name="OUT1BCL" addr="0x8"/>
887 <addr name="IN1BCL" addr="0xc"/>
888 <addr name="OUT2BCL" addr="0x10"/>
889 <addr name="IN2BCL" addr="0x14"/>
890 </reg>
891 <reg name="BCH" desc="Endpoint byte count MSB">
892 <addr name="OUT1BCH" addr="0x9"/>
893 <addr name="IN1BCH" addr="0xd"/>
894 <addr name="OUT2BCH" addr="0x11"/>
895 <addr name="IN2BCH" addr="0x15"/>
896 </reg>
897 <reg name="CON" desc="Endpoint configuration register">
898 <addr name="OUT1CON" addr="0xa"/>
899 <addr name="IN1CON" addr="0xe"/>
900 <addr name="OUT2CON" addr="0x12"/>
901 <addr name="IN2CON" addr="0x16"/>
902 <field name="EP_ENABLE" desc="" bitrange="7:7"/>
903 <field name="STALL" desc="" bitrange="6:6"/>
904 <field name="EP_TYPE" desc="" bitrange="3:2">
905 <value name="RESERVED" value="0x0" desc=""/>
906 <value name="ISOCHRONOUS" value="0x1" desc=""/>
907 <value name="BULK" value="0x2" desc=""/>
908 <value name="INTERRUPT" value="0x3" desc=""/>
909 </field>
910 <field name="SUBFIFOS" desc="" bitrange="1:0">
911 <value name="SINGLE" value="0x0" desc=""/>
912 <value name="DOUBLE" value="0x1" desc=""/>
913 <value name="TRIPLE" value="0x2" desc=""/>
914 <value name="QUAD" value="0x3" desc=""/>
915 </field>
916 </reg>
917 <reg name="CS" desc="Endpoint status register">
918 <addr name="OUT1CS" addr="0xb"/>
919 <addr name="IN1CS" addr="0xf"/>
920 <addr name="OUT2CS" addr="0x13"/>
921 <addr name="IN2CS" addr="0x17"/>
922 <field name="AUTO" desc="" bitrange="4:4"/>
923 <field name="NPACK1" desc="" bitrange="3:3"/>
924 <field name="NPACK0" desc="" bitrange="2:2"/>
925 <field name="BUSY" desc="" bitrange="1:1"/>
926 <field name="ERROR" desc="" bitrange="0:0"/>
927 </reg>
928 <reg name="FIFODAT" desc="Endpoint FIFO">
929 <addr name="FIFO1DAT" addr="0x84"/>
930 <addr name="FIFO2DAT" addr="0x88"/>
931 </reg>
932 <reg name="EP0DAT" desc="Endpoint 0 buffers each 64 bytes long.">
933 <addr name="EP0INDAT" addr="0x100"/>
934 <addr name="EP0OUTDAT" addr="0x140"/>
935 </reg>
936 <reg name="SETUPDAT" desc="SETUP packet buffer">
937 <addr name="SETUPDAT" addr="0x180"/>
938 </reg>
939 <reg name="EPIRQ" desc="Endpoint irq flag register">
940 <addr name="IN04IRQ" addr="0x188"/>
941 <addr name="OUT04IRQ" addr="0x18a"/>
942 <field name="EP_NUM" desc="" bitrange="2:0"/>
943 </reg>
944 <reg name="USBIRQ" desc="General usb core irq flags">
945 <addr name="USBIRQ" addr="0x18c"/>
946 <field name="HS" desc="Enter high speed operation. Set by core on connection." bitrange="5:5"/>
947 <field name="RESET" desc="Asserted on usb reset." bitrange="4:4"/>
948 <field name="SUSPEND" desc="" bitrange="3:3"/>
949 <field name="SETUP_TOKEN" desc="" bitrange="2:2"/>
950 <field name="SOF" desc="" bitrange="1:1"/>
951 <field name="SETUP_DATA" desc="Setup data are ready to be accessed in SETUPDAT buffer." bitrange="0:0"/>
952 </reg>
953 <reg name="EPIEN" desc="Endpoint interrupt enable register">
954 <addr name="IN04IEN" addr="0x194"/>
955 <addr name="OUT04IEN" addr="0x196"/>
956 <field name="EP_NUM" desc="" bitrange="2:0"/>
957 </reg>
958 <reg name="USBIEN" desc="General usb interrupts enable register">
959 <addr name="USBIEN" addr="0x198"/>
960 <field name="HS" desc="" bitrange="5:5"/>
961 <field name="RESET" desc="" bitrange="4:4"/>
962 <field name="SUSPEND" desc="" bitrange="3:3"/>
963 <field name="SETUP_TOKEN" desc="" bitrange="2:2"/>
964 <field name="SOF" desc="" bitrange="1:1"/>
965 <field name="SETUP_DATA" desc="" bitrange="0:0"/>
966 </reg>
967 <reg name="IVECT" desc="Interrupt vector register&#10;known (guessed) values:&#10;0x00 - SETUP&#10;0x10 - RESET&#10;0x14 - HS&#10;0x28 - EPs&#10;0xD8 - OTG">
968 <addr name="IVECT" addr="0x1a0"/>
969 </reg>
970 <reg name="ENDPRST" desc="Endpoint reset register">
971 <addr name="ENDPRST" addr="0x1a2"/>
972 <field name="FIFO_RESET" desc="" bitrange="6:6"/>
973 <field name="TOGGLE_RESET" desc="" bitrange="5:5"/>
974 <field name="DIR" desc="" bitrange="4:4">
975 <value name="OUT" value="0x0" desc=""/>
976 <value name="IN" value="0x1" desc=""/>
977 </field>
978 <field name="EP_NUM" desc="" bitrange="2:0"/>
979 </reg>
980 <reg name="USBCS" desc="">
981 <addr name="USBCS" addr="0x1a3"/>
982 <field name="SOFT_CONNECT" desc="" bitrange="6:6"/>
983 <field name="SIGRESUME" desc="" bitrange="5:5"/>
984 <field name="USBSPEED" desc="" bitrange="1:1"/>
985 <field name="HCLSMODE" desc="" bitrange="0:0"/>
986 </reg>
987 <reg name="FIFOCTRL" desc="">
988 <addr name="FIFOCTRL" addr="0x1a8"/>
989 <field name="CPU_ACCESS" desc="" bitrange="7:7"/>
990 <field name="DMA" desc="" bitrange="5:5"/>
991 <field name="DIR" desc="" bitrange="4:4">
992 <value name="OUT" value="0x0" desc=""/>
993 <value name="IN" value="0x1" desc=""/>
994 </field>
995 <field name="EP_NUM" desc="" bitrange="2:0"/>
996 </reg>
997 <reg name="OTGIRQ" desc="">
998 <addr name="OTGIRQ" addr="0x1bc"/>
999 <field name="PERIPH" desc="" bitrange="4:4"/>
1000 <field name="VBUSERR" desc="" bitrange="3:3"/>
1001 <field name="LOCSOFT" desc="" bitrange="2:2"/>
1002 <field name="SPRDET" desc="" bitrange="1:1"/>
1003 <field name="OTG_IDLE" desc="" bitrange="0:0"/>
1004 </reg>
1005 <reg name="OTGSTATUS" desc="">
1006 <addr name="OTGSTATUS" addr="0x1bf"/>
1007 </reg>
1008 <reg name="OTGIEN" desc="OTG interrupt enable register">
1009 <addr name="OTGIEN" addr="0x1c0"/>
1010 </reg>
1011 <reg name="HCMAXPCKL" desc="High speed max packed size LSB">
1012 <addr name="HCIN1MAXPCKL" addr="0x1e2"/>
1013 <addr name="HCOUT2MAXPCKL" addr="0x3e4"/>
1014 </reg>
1015 <reg name="STADDR" desc="Endpoint buffer start address">
1016 <addr name="OUT1STADDR" addr="0x304"/>
1017 <addr name="IN2STADDR" addr="0x348"/>
1018 </reg>
1019 <reg name="USBEIRQ" desc="USB extended irq register">
1020 <addr name="USBEIRQ" addr="0x400"/>
1021 <field name="USB" desc="" bitrange="7:7"/>
1022 <field name="WAKEUP" desc="" bitrange="6:6"/>
1023 <field name="RESUME" desc="" bitrange="5:5"/>
1024 <field name="CONDISCON" desc="" bitrange="4:4"/>
1025 <field name="USBIEN" desc="" bitrange="3:3"/>
1026 <field name="WAKEUPIEN" desc="" bitrange="2:2"/>
1027 <field name="RESUMEIEN" desc="" bitrange="1:1"/>
1028 <field name="CONDISCONIEN" desc="" bitrange="0:0"/>
1029 </reg>
1030 <reg name="USBERST" desc="">
1031 <addr name="USBERST" addr="0x404"/>
1032 </reg>
1033 <reg name="DMAEPSEL" desc="">
1034 <addr name="DMAEPSEL" addr="0x40c"/>
1035 <field name="EP_SEL" desc="" bitrange="31:0">
1036 <value name="UNKNOWN" value="0x0" desc=""/>
1037 <value name="EP1_IN" value="0x1" desc=""/>
1038 <value name="EP1_OUT" value="0x3" desc=""/>
1039 <value name="EP2_IN" value="0x4" desc=""/>
1040 <value name="EP2_OUT" value="0xc" desc=""/>
1041 </field>
1042 </reg>
1043 </dev>
1044 <dev name="YUV2RGB" long_name="Color Space Conversion Accelerator" desc="" version="">
1045 <addr name="YUV2RGB" addr="0xb00f0000"/>
1046 <reg name="CTL" desc="">
1047 <addr name="CTL" addr="0x0"/>
1048 <field name="RESERVED" desc="" bitrange="31:22"/>
1049 <field name="RFBM" desc="Read fifo block mode." bitrange="21:21"/>
1050 <field name="WFBM" desc="Write fifo block mode" bitrange="20:20"/>
1051 <field name="EN" desc="RGB Decoder enable." bitrange="19:19"/>
1052 <field name="FES" desc="Fifo empty status." bitrange="18:18"/>
1053 <field name="WDCS" desc="Write Data/Command Select" bitrange="17:16">
1054 <value name="CMD" value="0x0" desc="Write LCD register address"/>
1055 <value name="DATA" value="0x1" desc="Write LCD register data"/>
1056 <value name="RGB" value="0x2" desc="RGB565 Data FrameBuffer Transfer"/>
1057 <value name="YUV" value="0x3" desc="YCbCr/YUV Data FrameBuffer Transfer"/>
1058 </field>
1059 <field name="DEST" desc="RGB Decoder Destination." bitrange="15:15"/>
1060 <field name="FORMATS" desc="RGB Format" bitrange="13:11">
1061 <value name="RGB565_1" value="0x0" desc="16bit (RGB 565 1transfer)"/>
1062 <value name="RGB666_1" value="0x1" desc="18bit (RGB 666 1transfer)"/>
1063 <value name="RGB565_2" value="0x2" desc="8bit (RGB 565 2transfers)"/>
1064 <value name="RGB666_2" value="0x3" desc="9bit (RGB 666 2transfers)"/>
1065 <value name="RGB888_3" value="0x4" desc="8bit (RGB 888 3transfers)"/>
1066 <value name="RGB666_3" value="0x5" desc="6bit (RGB 666 3transfers)"/>
1067 </field>
1068 <field name="SEQ" desc="RGB Sequence" bitrange="10:10">
1069 <value name="RGB" value="0x0" desc=""/>
1070 <value name="BGR" value="0x1" desc=""/>
1071 </field>
1072 <field name="FWCS" desc="FIFO write channel select." bitrange="9:9">
1073 <value name="SPECIAL" value="0x0" desc=""/>
1074 <value name="AHB" value="0x1" desc=""/>
1075 </field>
1076 <field name="FRCS" desc="FIFO read channel select" bitrange="8:8">
1077 <value name="SPECIAL" value="0x0" desc=""/>
1078 <value name="AHB" value="0x1" desc=""/>
1079 </field>
1080 <field name="EMDE" desc="FIFO Empty (Write) DRQ Enable." bitrange="7:7"/>
1081 <field name="EMIE" desc="FIFO Empty (Write) IRQ Enable." bitrange="6:6"/>
1082 <field name="FUDE" desc="FIFO Full (Read) DRQ Enable." bitrange="5:5"/>
1083 <field name="FUIE" desc="FIFO Full (Read) IRQ Enable." bitrange="4:4"/>
1084 <field name="EMCO" desc="FIFO Empty (Write) Condition." bitrange="3:3">
1085 <value name="EMPTY_4_8" value="0x0" desc=""/>
1086 <value name="EMPTY_0_8" value="0x1" desc=""/>
1087 </field>
1088 <field name="EMIP" desc="FIFO Empty (Write) IRQ Pending Bit." bitrange="2:2"/>
1089 <field name="FUIP" desc="FIFO Full (Read) IRQ Pending Bit." bitrange="1:1"/>
1090 <field name="ERP" desc="FIFO Error Pending Bit. Write 1 to the bit to clear it and reset the FIFO." bitrange="0:0"/>
1091 </reg>
1092 <reg name="FIFODATA" desc="">
1093 <addr name="FIFODATA" addr="0x4"/>
1094 </reg>
1095 <reg name="CLKCTL" desc="">
1096 <addr name="CLKCTL" addr="0x8"/>
1097 </reg>
1098 <reg name="FRAMECOUNT" desc="">
1099 <addr name="FRAMECOUNT" addr="0xc"/>
1100 </reg>
1101 </dev>
1102</soc>
diff --git a/utils/regtools/desc/regs-atj213x.xml b/utils/regtools/desc/regs-atj213x.xml
index cca7db9fc0..9df78d3280 100644
--- a/utils/regtools/desc/regs-atj213x.xml
+++ b/utils/regtools/desc/regs-atj213x.xml
@@ -1,1102 +1,3713 @@
1<?xml version="1.0"?> 1<?xml version="1.0"?>
2<soc name="atj213x" desc="Actions atj213x"> 2<soc version="2">
3 <dev name="ADC" long_name="Analog to Digital Converter" desc="" version="1.0"> 3 <name>atj213x</name>
4 <addr name="ADC" addr="0xb0110000"/> 4 <title>Actions atj213x</title>
5 </dev> 5 <author>Marcin Bukat</author>
6 <dev name="ATA" long_name="" desc="" version="1.0"> 6 <node>
7 <addr name="ATA" addr="0xb0090000"/> 7 <name>ADC</name>
8 <reg name="CONFIG" desc=""> 8 <title>Analog to Digital Converter</title>
9 <addr name="CONFIG" addr="0x0"/> 9 <instance>
10 </reg> 10 <name>ADC</name>
11 <reg name="UDMACTL" desc=""> 11 <address>0xb0110000</address>
12 <addr name="UDMACTL" addr="0x4"/> 12 </instance>
13 </reg> 13 </node>
14 <reg name="DATA" desc=""> 14 <node>
15 <addr name="DATA" addr="0x8"/> 15 <name>ATA</name>
16 </reg> 16 <instance>
17 <reg name="FEATURE" desc=""> 17 <name>ATA</name>
18 <addr name="FEATURE" addr="0xc"/> 18 <address>0xb0090000</address>
19 </reg> 19 </instance>
20 <reg name="SECCNT" desc=""> 20 <node>
21 <addr name="SECCNT" addr="0x10"/> 21 <name>CONFIG</name>
22 </reg> 22 <instance>
23 <reg name="SECNUM" desc=""> 23 <name>CONFIG</name>
24 <addr name="SECNUM" addr="0x14"/> 24 <address>0x0</address>
25 </reg> 25 </instance>
26 <reg name="CLDLOW" desc=""> 26 <register/>
27 <addr name="CLDL" addr="0x18"/> 27 </node>
28 </reg> 28 <node>
29 <reg name="CLDHI" desc=""> 29 <name>UDMACTL</name>
30 <addr name="CLDHIGH" addr="0x1c"/> 30 <instance>
31 </reg> 31 <name>UDMACTL</name>
32 <reg name="HEAD" desc=""> 32 <address>0x4</address>
33 <addr name="HEAD" addr="0x20"/> 33 </instance>
34 </reg> 34 <register/>
35 <reg name="CMD" desc=""> 35 </node>
36 <addr name="CMD" addr="0x24"/> 36 <node>
37 </reg> 37 <name>DATA</name>
38 <reg name="BYTECNT" desc=""> 38 <instance>
39 <addr name="BYTECNT" addr="0x28"/> 39 <name>DATA</name>
40 </reg> 40 <address>0x8</address>
41 <reg name="FIFOCTL" desc=""> 41 </instance>
42 <addr name="FIFOCTL" addr="0x2c"/> 42 <register/>
43 </reg> 43 </node>
44 <reg name="FIFOCFG" desc=""> 44 <node>
45 <addr name="FIFOCFG" addr="0x30"/> 45 <name>FEATURE</name>
46 </reg> 46 <instance>
47 <reg name="ADDRDEC" desc=""> 47 <name>FEATURE</name>
48 <addr name="ADDRDEC" addr="0x34"/> 48 <address>0xc</address>
49 </reg> 49 </instance>
50 <reg name="IRQCTL" desc=""> 50 <register/>
51 <addr name="IRQCTL" addr="0x38"/> 51 </node>
52 </reg> 52 <node>
53 </dev> 53 <name>SECCNT</name>
54 <dev name="BOOT" long_name="" desc="" version=""> 54 <instance>
55 <addr name="BOOT" addr="0xb0038000"/> 55 <name>SECCNT</name>
56 <reg name="NORCTL" desc=""> 56 <address>0x10</address>
57 <addr name="NORCTL" addr="0x0"/> 57 </instance>
58 </reg> 58 <register/>
59 <reg name="BROMCTL" desc=""> 59 </node>
60 <addr name="BROMCTL" addr="0x4"/> 60 <node>
61 </reg> 61 <name>SECNUM</name>
62 <reg name="CHIPID" desc=""> 62 <instance>
63 <addr name="CHIPID" addr="0x8"/> 63 <name>SECNUM</name>
64 </reg> 64 <address>0x14</address>
65 </dev> 65 </instance>
66 <dev name="BT" long_name="" desc="" version=""> 66 <register/>
67 <addr name="BT" addr="0xb00d0000"/> 67 </node>
68 </dev> 68 <node>
69 <dev name="CMU" long_name="Clock Management Unit" desc="" version="1.0"> 69 <name>CLDLOW</name>
70 <addr name="CMU" addr="0xb0010000"/> 70 <instance>
71 <reg name="COREPLL" desc=""> 71 <name>CLDL</name>
72 <addr name="COREPLL" addr="0x0"/> 72 <address>0x18</address>
73 <field name="RESERVED31_11" desc="" bitrange="31:11"/> 73 </instance>
74 <field name="CPBY" desc="Core PLL Bypass " bitrange="10:10"/> 74 <register/>
75 <field name="CPBI" desc="Core PLL Bias " bitrange="9:8"/> 75 </node>
76 <field name="CPEN" desc="Core PLL Enable " bitrange="7:7"/> 76 <node>
77 <field name="HOEN" desc="High Oscillator Enable" bitrange="6:6"/> 77 <name>CLDHI</name>
78 <field name="CPCK" desc="COREPLLout = CPCK * 6 (MHz) (in range 12 - 378MHz)" bitrange="5:0"/> 78 <instance>
79 </reg> 79 <name>CLDHIGH</name>
80 <reg name="DSPPLL" desc=""> 80 <address>0x1c</address>
81 <addr name="DSPPLL" addr="0x4"/> 81 </instance>
82 <field name="RESERVED31_9" desc="" bitrange="31:9"/> 82 <register/>
83 <field name="DPBI" desc="DSP PLL Bias" bitrange="8:7"/> 83 </node>
84 <field name="DPEN" desc="DSP PLL Enable" bitrange="6:6"/> 84 <node>
85 <field name="DPCK" desc="DSPPLLout = DPCK * 6 (MHz) (in range 12-378MHz)" bitrange="5:0"/> 85 <name>HEAD</name>
86 </reg> 86 <instance>
87 <reg name="AUDIOPLL" desc=""> 87 <name>HEAD</name>
88 <addr name="AUDIOPLL" addr="0x8"/> 88 <address>0x20</address>
89 <field name="RESERVED31_12" desc="" bitrange="31:12"/> 89 </instance>
90 <field name="ADCPLL" desc="Audio PLL CLk Control" bitrange="11:11"/> 90 <register/>
91 <field name="ADCCLK" desc="ADC Clock Divisor, output is FS*256" bitrange="10:8"/> 91 </node>
92 <field name="RESERVED7" desc="" bitrange="7:7"/> 92 <node>
93 <field name="APBI" desc="Audio PLL Bias" bitrange="6:5"/> 93 <name>CMD</name>
94 <field name="APEN" desc="Audio PLL Enable" bitrange="4:4"/> 94 <instance>
95 <field name="DACPLL" desc="DAC PLL CLk Control" bitrange="3:3"/> 95 <name>CMD</name>
96 <field name="DACCLK" desc="DAC Clock Divisor, output is FS*256" bitrange="2:0"/> 96 <address>0x24</address>
97 </reg> 97 </instance>
98 <reg name="BUSCLK" desc="Bus CLK Control Register"> 98 <register/>
99 <addr name="BUSCLK" addr="0xc"/> 99 </node>
100 <field name="KEYE" desc="Key Wakeup Enable" bitrange="31:31"/> 100 <node>
101 <field name="ALME" desc="Alarm Wakeup Enable" bitrange="30:30"/> 101 <name>BYTECNT</name>
102 <field name="SIRE" desc="SIRQ Wakeup Enable" bitrange="29:29"/> 102 <instance>
103 <field name="RESERVED28" desc="" bitrange="28:28"/> 103 <name>BYTECNT</name>
104 <field name="USBE" desc="Usb Wakeup Enable" bitrange="27:27"/> 104 <address>0x28</address>
105 <field name="RESERVED26_12" desc="" bitrange="26:12"/> 105 </instance>
106 <field name="PCLKDIV" desc="Peripheral CLK Divisor" bitrange="11:8"/> 106 <register/>
107 <field name="CORECLKS" desc="CPU Clock Selection" bitrange="7:6"/> 107 </node>
108 <field name="SCLKDIV" desc="System Clock Divisor" bitrange="5:4"/> 108 <node>
109 <field name="CCLKDIV" desc="CPU Clock Divisor" bitrange="3:2"/> 109 <name>FIFOCTL</name>
110 <field name="DCEN" desc="Core CLK DC Enable" bitrange="1:1"/> 110 <instance>
111 </reg> 111 <name>FIFOCTL</name>
112 <reg name="SDRCLK" desc="SDRAM Interface CLK Control Register"> 112 <address>0x2c</address>
113 <addr name="SDRCLK" addr="0x10"/> 113 </instance>
114 <field name="RESERVED31_2" desc="" bitrange="31:2"/> 114 <register/>
115 <field name="SDRDIV" desc="" bitrange="1:0"/> 115 </node>
116 </reg> 116 <node>
117 <reg name="NANDCLK" desc="NAND Interface CLK Control Register"> 117 <name>FIFOCFG</name>
118 <addr name="NANDCLK" addr="0x18"/> 118 <instance>
119 <field name="RESERVED31_4" desc="" bitrange="31:4"/> 119 <name>FIFOCFG</name>
120 <field name="NANDDIV" desc="" bitrange="3:0"/> 120 <address>0x30</address>
121 </reg> 121 </instance>
122 <reg name="SDCLK" desc="SD Interface CLK Control Register&#10;"> 122 <register/>
123 <addr name="SDCLK" addr="0x1c"/> 123 </node>
124 <field name="RESERVED31_6" desc="" bitrange="31:6"/> 124 <node>
125 <field name="CKEN" desc="SD Interface Clock Enable" bitrange="5:5"/> 125 <name>ADDRDEC</name>
126 <field name="D128" desc="Enable Divide 128 circuit" bitrange="4:4"/> 126 <instance>
127 <field name="SDDIV" desc="" bitrange="3:0"/> 127 <name>ADDRDEC</name>
128 </reg> 128 <address>0x34</address>
129 <reg name="MHACLK" desc="MHA CLK Control Register"> 129 </instance>
130 <addr name="MHACLK" addr="0x20"/> 130 <register/>
131 <field name="RESERVED31_4" desc="" bitrange="31:4"/> 131 </node>
132 <field name="MHADIV" desc="" bitrange="3:0"/> 132 <node>
133 </reg> 133 <name>IRQCTL</name>
134 <reg name="UART2CLK" desc="Uart2 CLK Control Register"> 134 <instance>
135 <addr name="UART2CLK" addr="0x2c"/> 135 <name>IRQCTL</name>
136 <field name="RESERVED31_17" desc="" bitrange="31:17"/> 136 <address>0x38</address>
137 <field name="U2EN" desc="Uart2 Clock Enable &#10;" bitrange="16:16"/> 137 </instance>
138 <field name="UART2DIV" desc="" bitrange="15:0"/> 138 <register/>
139 </reg> 139 </node>
140 <reg name="DMACLK" desc="DMA CLK Control Register"> 140 </node>
141 <addr name="DMACLK" addr="0x30"/> 141 <node>
142 <field name="RESERVED31_4" desc="" bitrange="31:4"/> 142 <name>BOOT</name>
143 <field name="D7EN" desc="DMA 7 (Special Channel) Clock Enable" bitrange="3:3"/> 143 <instance>
144 <field name="D6EN" desc="DMA 6 (Special Channel) Clock Enable" bitrange="2:2"/> 144 <name>BOOT</name>
145 <field name="D5EN" desc="DMA 5 (Special Channel) Clock Enable" bitrange="1:1"/> 145 <address>0xb0038000</address>
146 <field name="D4EN" desc="DMA 4 (Special Channel) Clock Enable" bitrange="0:0"/> 146 </instance>
147 </reg> 147 <node>
148 <reg name="FMCLK" desc="FM CLK Control Register"> 148 <name>NORCTL</name>
149 <addr name="FMCLK" addr="0x34"/> 149 <instance>
150 <field name="RESERVED31_6" desc="" bitrange="31:6"/> 150 <name>NORCTL</name>
151 <field name="BCKE" desc="PWM Back Light clock Enable" bitrange="5:5"/> 151 <address>0x0</address>
152 <field name="BCKS" desc="Back Light CLK source select" bitrange="4:4"/> 152 </instance>
153 <field name="BCKCON" desc="Divided PWM Back Light Special Clock Control" bitrange="3:2"/> 153 <register/>
154 <field name="CLKS" desc="FM Clock Output Selection" bitrange="1:1"/> 154 </node>
155 <field name="OUTE" desc="FM Clock Output Enable (From Test Pin)" bitrange="0:0"/> 155 <node>
156 </reg> 156 <name>BROMCTL</name>
157 <reg name="MCACLK" desc="MCA CLK Control Register"> 157 <instance>
158 <addr name="MCACLK" addr="0x38"/> 158 <name>BROMCTL</name>
159 <field name="RESERVED31_4" desc="" bitrange="31:4"/> 159 <address>0x4</address>
160 <field name="MCADIV" desc="" bitrange="3:0"/> 160 </instance>
161 </reg> 161 <register/>
162 <reg name="DEVCLKEN" desc="Device CLK Control Register"> 162 </node>
163 <addr name="DEVCLKEN" addr="0x80"/> 163 <node>
164 <field name="RESERVED31_27" desc="" bitrange="31:27"/> 164 <name>CHIPID</name>
165 <field name="GPIO" desc="" bitrange="26:26"/> 165 <instance>
166 <field name="KEY" desc="" bitrange="25:25"/> 166 <name>CHIPID</name>
167 <field name="RESERVED24" desc="" bitrange="24:24"/> 167 <address>0x8</address>
168 <field name="I2C" desc="" bitrange="23:23"/> 168 </instance>
169 <field name="UART" desc="" bitrange="22:22"/> 169 <register/>
170 <field name="RESERVED21_19" desc="" bitrange="21:19"/> 170 </node>
171 <field name="ADC" desc="" bitrange="18:18"/> 171 </node>
172 <field name="DAC" desc="" bitrange="17:17"/> 172 <node>
173 <field name="DSPC" desc="" bitrange="16:16"/> 173 <name>BT</name>
174 <field name="MCA" desc="" bitrange="15:15"/> 174 <instance>
175 <field name="MHA" desc="" bitrange="14:14"/> 175 <name>BT</name>
176 <field name="USBC" desc="" bitrange="13:13"/> 176 <address>0xb00d0000</address>
177 <field name="RESERVED12" desc="" bitrange="12:12"/> 177 </instance>
178 <field name="SD" desc="" bitrange="11:11"/> 178 </node>
179 <field name="RESERVED10" desc="" bitrange="10:10"/> 179 <node>
180 <field name="NAND" desc="" bitrange="9:9"/> 180 <name>CMU</name>
181 <field name="DMAC" desc="" bitrange="8:8"/> 181 <title>Clock Management Unit</title>
182 <field name="PCNT" desc="" bitrange="7:7"/> 182 <instance>
183 <field name="SDRM" desc="" bitrange="6:6"/> 183 <name>CMU</name>
184 <field name="SDRC" desc="" bitrange="5:5"/> 184 <address>0xb0010000</address>
185 <field name="DSPM" desc="" bitrange="4:4"/> 185 </instance>
186 <field name="RESERVED3" desc="" bitrange="3:3"/> 186 <node>
187 <field name="RMOC" desc="" bitrange="2:2"/> 187 <name>COREPLL</name>
188 <field name="YUV" desc="" bitrange="1:1"/> 188 <instance>
189 <field name="RESERVED0" desc="" bitrange="0:0"/> 189 <name>COREPLL</name>
190 </reg> 190 <address>0x0</address>
191 <reg name="DEVRST" desc="Device Reset Control Register"> 191 </instance>
192 <addr name="DEVRST" addr="0x84"/> 192 <register>
193 <field name="RESERVED31" desc="" bitrange="31:31"/> 193 <field>
194 <field name="GPIO" desc="" bitrange="30:30"/> 194 <name>RESERVED31_11</name>
195 <field name="KEY" desc="" bitrange="29:29"/> 195 <position>11</position>
196 <field name="RESERVED28" desc="" bitrange="28:28"/> 196 <width>21</width>
197 <field name="I2C" desc="" bitrange="27:27"/> 197 </field>
198 <field name="UART" desc="" bitrange="26:26"/> 198 <field>
199 <field name="RESERVED25_23" desc="" bitrange="25:23"/> 199 <name>CPBY</name>
200 <field name="ADC" desc="" bitrange="22:22"/> 200 <desc>Core PLL Bypass </desc>
201 <field name="DAC" desc="" bitrange="21:21"/> 201 <position>10</position>
202 <field name="DSPC" desc="DSP control block reset" bitrange="20:20"/> 202 </field>
203 <field name="INTC" desc="" bitrange="19:19"/> 203 <field>
204 <field name="RTC" desc="" bitrange="18:18"/> 204 <name>CPBI</name>
205 <field name="PMU" desc="" bitrange="17:17"/> 205 <desc>Core PLL Bias </desc>
206 <field name="RESERVED16_14" desc="" bitrange="16:14"/> 206 <position>8</position>
207 <field name="DSPM" desc="SRAM DSP MEM reset" bitrange="13:13"/> 207 <width>2</width>
208 <field name="TVENC" desc="" bitrange="12:12"/> 208 </field>
209 <field name="YUV" desc="" bitrange="11:11"/> 209 <field>
210 <field name="MCA" desc="" bitrange="10:10"/> 210 <name>CPEN</name>
211 <field name="USB" desc="" bitrange="9:9"/> 211 <desc>Core PLL Enable </desc>
212 <field name="RESERVED8" desc="" bitrange="8:8"/> 212 <position>7</position>
213 <field name="MHA" desc="" bitrange="7:7"/> 213 </field>
214 <field name="SD" desc="" bitrange="6:6"/> 214 <field>
215 <field name="NAND" desc="" bitrange="5:5"/> 215 <name>HOEN</name>
216 <field name="RESERVED4" desc="" bitrange="4:4"/> 216 <desc>High Oscillator Enable</desc>
217 <field name="DMAC" desc="" bitrange="3:3"/> 217 <position>6</position>
218 <field name="PCNT" desc="" bitrange="2:2"/> 218 </field>
219 <field name="RESERVED1" desc="" bitrange="1:1"/> 219 <field>
220 <field name="SDR" desc="SDRAM Control register and SDRAM block Reset" bitrange="0:0"/> 220 <name>CPCK</name>
221 </reg> 221 <desc>COREPLLout = CPCK * 6 (MHz) (in range 12 - 378MHz)</desc>
222 </dev> 222 <position>0</position>
223 <dev name="DAC" long_name="Digital Analog Converter" desc="" version="1.0"> 223 <width>6</width>
224 <addr name="DAC" addr="0xb0100000"/> 224 </field>
225 </dev> 225 </register>
226 <dev name="DMAC" long_name="Direct Memory Access Controller" desc="Channels 0-3 work with retular AHB bus, channels 4-7 work with 'special' bus." version=""> 226 </node>
227 <addr name="DMAC" addr="0xb0060000"/> 227 <node>
228 <reg name="CTL" desc=""> 228 <name>DSPPLL</name>
229 <addr name="CTL" addr="0x0"/> 229 <instance>
230 </reg> 230 <name>DSPPLL</name>
231 <reg name="IRQEN" desc=""> 231 <address>0x4</address>
232 <addr name="IRQEN" addr="0x4"/> 232 </instance>
233 </reg> 233 <register>
234 <reg name="IRQPD" desc=""> 234 <field>
235 <addr name="IRQPD" addr="0x8"/> 235 <name>RESERVED31_9</name>
236 </reg> 236 <position>9</position>
237 <reg name="DMA_MODE" desc=""> 237 <width>23</width>
238 <formula string="0x100+n*0x20"/> 238 </field>
239 <addr name="DMA_MODE0" addr="0x100"/> 239 <field>
240 <addr name="DMA_MODE1" addr="0x120"/> 240 <name>DPBI</name>
241 <addr name="DMA_MODE2" addr="0x140"/> 241 <desc>DSP PLL Bias</desc>
242 <addr name="DMA_MODE3" addr="0x160"/> 242 <position>7</position>
243 <addr name="DMA_MODE4" addr="0x180"/> 243 <width>2</width>
244 <addr name="DMA_MODE5" addr="0x1a0"/> 244 </field>
245 <addr name="DMA_MODE6" addr="0x1c0"/> 245 <field>
246 <addr name="DMA_MODE7" addr="0x1e0"/> 246 <name>DPEN</name>
247 <field name="DBURLEN" desc="Destination burst length. If burst lenght is 4 or 8 DDIR must be 0, DFXA must be 0, DDSP must be 0, DCOL must be 0. Burst must not cross a 1kB address boundary." bitrange="31:29"> 247 <desc>DSP PLL Enable</desc>
248 <value name="SINGLE" value="0x0" desc=""/> 248 <position>6</position>
249 <value name="INCR4" value="0x3" desc=""/> 249 </field>
250 <value name="INCR8" value="0x5" desc=""/> 250 <field>
251 </field> 251 <name>DPCK</name>
252 <field name="RELO" desc="DMA Reload Bit." bitrange="28:28"/> 252 <desc>DSPPLLout = DPCK * 6 (MHz) (in range 12-378MHz)</desc>
253 <field name="DDSP" desc="Destination DSP mode.&#10;" bitrange="27:27"/> 253 <position>0</position>
254 <field name="DCOL" desc="Destination Column Mode." bitrange="26:26"/> 254 <width>6</width>
255 <field name="DDIR" desc="Destination address direction. If DBURLEN is INCR4 or INCR8 only INCREASE is allowed." bitrange="25:25"> 255 </field>
256 <value name="INCREASE" value="0x0" desc=""/> 256 </register>
257 <value name="DECREASE" value="0x1" desc=""/> 257 </node>
258 </field> 258 <node>
259 <field name="DFXA" desc="Destination Fixed Address bit." bitrange="24:24"> 259 <name>AUDIOPLL</name>
260 <value name="NOT_FIXED" value="0x0" desc=""/> 260 <instance>
261 <value name="FIXED" value="0x1" desc=""/> 261 <name>AUDIOPLL</name>
262 </field> 262 <address>0x8</address>
263 <field name="DTRG" desc="Destination DRQ Trig Source." bitrange="23:19"> 263 </instance>
264 <value name="DAC" value="0x6" desc=""/> 264 <register>
265 <value name="SDRAM" value="0x10" desc=""/> 265 <field>
266 <value name="IRAM" value="0x11" desc=""/> 266 <name>RESERVED31_12</name>
267 <value name="SD" value="0x16" desc=""/> 267 <position>12</position>
268 <value name="OTG" value="0x17" desc=""/> 268 <width>20</width>
269 <value name="LCM" value="0x18" desc=""/> 269 </field>
270 </field> 270 <field>
271 <field name="DTRANWID" desc="" bitrange="18:17"> 271 <name>ADCPLL</name>
272 <value name="WIDTH8" value="0x0" desc=""/> 272 <desc>Audio PLL CLk Control</desc>
273 <value name="WIDTH16" value="0x1" desc=""/> 273 <position>11</position>
274 <value name="WIDTH32" value="0x2" desc=""/> 274 </field>
275 </field> 275 <field>
276 <field name="DFXS" desc="If DFXS=0, DMA will transfer in 8bit mode when remain counter is less than DTRANWID. &#10;If DFXS=1, DMA will always transfer in DTRANWID. &#10;" bitrange="16:16"/> 276 <name>ADCCLK</name>
277 <field name="SBURLEN" desc="Source burst length. If burst lenght is 4 or 8 DDIR must be 0, DFXA must be 0, DDSP must be 0, DCOL must be 0. Burst must not cross a 1kB address boundary." bitrange="15:13"> 277 <desc>ADC Clock Divisor, output is FS*256</desc>
278 <value name="SINGLE" value="0x0" desc=""/> 278 <position>8</position>
279 <value name="INCR4" value="0x3" desc=""/> 279 <width>3</width>
280 <value name="INCR8" value="0x5" desc=""/> 280 </field>
281 </field> 281 <field>
282 <field name="SDSP" desc="Source DSP mode. &#10;" bitrange="11:11"/> 282 <name>RESERVED7</name>
283 <field name="SCOL" desc="Source Column Mode." bitrange="10:10"/> 283 <position>7</position>
284 <field name="SDIR" desc="Source address direction. If SBURLEN is INCR4 or INCR8 only INCREASE is allowed." bitrange="9:9"> 284 </field>
285 <value name="INCREASE" value="0x0" desc=""/> 285 <field>
286 <value name="DECREASE" value="0x1" desc=""/> 286 <name>APBI</name>
287 </field> 287 <desc>Audio PLL Bias</desc>
288 <field name="SFXA" desc="Source Fixed Addres bit." bitrange="8:8"> 288 <position>5</position>
289 <value name="NOT_FIXED" value="0x0" desc=""/> 289 <width>2</width>
290 <value name="FIXED" value="0x1" desc=""/> 290 </field>
291 </field> 291 <field>
292 <field name="STRG" desc="DRQ trig source." bitrange="7:3"> 292 <name>APEN</name>
293 <value name="DAC" value="0x6" desc=""/> 293 <desc>Audio PLL Enable</desc>
294 <value name="SDRAM" value="0x10" desc=""/> 294 <position>4</position>
295 <value name="IRAM" value="0x11" desc=""/> 295 </field>
296 <value name="SD" value="0x16" desc=""/> 296 <field>
297 <value name="OTG" value="0x17" desc=""/> 297 <name>DACPLL</name>
298 <value name="LCM" value="0x18" desc=""/> 298 <desc>DAC PLL CLk Control</desc>
299 </field> 299 <position>3</position>
300 <field name="STRANWID" desc="" bitrange="2:1"> 300 </field>
301 <value name="WIDTH8" value="0x0" desc=""/> 301 <field>
302 <value name="WIDTH16" value="0x1" desc=""/> 302 <name>DACCLK</name>
303 <value name="WIDTH32" value="0x2" desc=""/> 303 <desc>DAC Clock Divisor, output is FS*256</desc>
304 </field> 304 <position>0</position>
305 <field name="SFXS" desc="Source Fix Size. If DFXS=0, DMA will transfer in 8bit mode when remain counter is less than STRANWID. If SFXS=1, DMA will always transfer in STRANWID." bitrange="0:0"/> 305 <width>3</width>
306 </reg> 306 </field>
307 <reg name="DMA_SRC" desc=""> 307 </register>
308 <formula string="0x104+n*0x20"/> 308 </node>
309 <addr name="DMA_SRC0" addr="0x104"/> 309 <node>
310 <addr name="DMA_SRC1" addr="0x124"/> 310 <name>BUSCLK</name>
311 <addr name="DMA_SRC2" addr="0x144"/> 311 <instance>
312 <addr name="DMA_SRC3" addr="0x164"/> 312 <name>BUSCLK</name>
313 <addr name="DMA_SRC4" addr="0x184"/> 313 <address>0xc</address>
314 <addr name="DMA_SRC5" addr="0x1a4"/> 314 </instance>
315 <addr name="DMA_SRC6" addr="0x1c4"/> 315 <register>
316 <addr name="DMA_SRC7" addr="0x1e4"/> 316 <desc>Bus CLK Control Register</desc>
317 </reg> 317 <field>
318 <reg name="DMA_DST" desc=""> 318 <name>KEYE</name>
319 <formula string="0x108+n*0x20"/> 319 <desc>Key Wakeup Enable</desc>
320 <addr name="DMA_DST0" addr="0x108"/> 320 <position>31</position>
321 <addr name="DMA_DST1" addr="0x128"/> 321 </field>
322 <addr name="DMA_DST2" addr="0x148"/> 322 <field>
323 <addr name="DMA_DST3" addr="0x168"/> 323 <name>ALME</name>
324 <addr name="DMA_DST4" addr="0x188"/> 324 <desc>Alarm Wakeup Enable</desc>
325 <addr name="DMA_DST5" addr="0x1a8"/> 325 <position>30</position>
326 <addr name="DMA_DST6" addr="0x1c8"/> 326 </field>
327 <addr name="DMA_DST7" addr="0x1e8"/> 327 <field>
328 </reg> 328 <name>SIRE</name>
329 <reg name="DMA_CNT" desc=""> 329 <desc>SIRQ Wakeup Enable</desc>
330 <formula string="0x10c+n*0x20"/> 330 <position>29</position>
331 <addr name="DMA_CNT0" addr="0x10c"/> 331 </field>
332 <addr name="DMA_CNT1" addr="0x12c"/> 332 <field>
333 <addr name="DMA_CNT2" addr="0x14c"/> 333 <name>RESERVED28</name>
334 <addr name="DMA_CNT3" addr="0x16c"/> 334 <position>28</position>
335 <addr name="DMA_CNT4" addr="0x18c"/> 335 </field>
336 <addr name="DMA_CNT5" addr="0x1ac"/> 336 <field>
337 <addr name="DMA_CNT6" addr="0x1cc"/> 337 <name>USBE</name>
338 <addr name="DMA_CNT7" addr="0x1ec"/> 338 <desc>Usb Wakeup Enable</desc>
339 </reg> 339 <position>27</position>
340 <reg name="DMA_REM" desc=""> 340 </field>
341 <formula string="0x110+n*0x20"/> 341 <field>
342 <addr name="DMA_REM0" addr="0x110"/> 342 <name>RESERVED26_12</name>
343 <addr name="DMA_REM1" addr="0x130"/> 343 <position>12</position>
344 <addr name="DMA_REM2" addr="0x150"/> 344 <width>15</width>
345 <addr name="DMA_REM3" addr="0x170"/> 345 </field>
346 <addr name="DMA_REM4" addr="0x190"/> 346 <field>
347 <addr name="DMA_REM5" addr="0x1b0"/> 347 <name>PCLKDIV</name>
348 <addr name="DMA_REM6" addr="0x1d0"/> 348 <desc>Peripheral CLK Divisor</desc>
349 <addr name="DMA_REM7" addr="0x1f0"/> 349 <position>8</position>
350 </reg> 350 <width>4</width>
351 <reg name="DMA_CMD" desc=""> 351 </field>
352 <formula string="0x114+n*0x20"/> 352 <field>
353 <addr name="DMA_CMD0" addr="0x114"/> 353 <name>CORECLKS</name>
354 <addr name="DMA_CMD1" addr="0x134"/> 354 <desc>CPU Clock Selection</desc>
355 <addr name="DMA_CMD2" addr="0x154"/> 355 <position>6</position>
356 <addr name="DMA_CMD3" addr="0x174"/> 356 <width>2</width>
357 <addr name="DMA_CMD4" addr="0x194"/> 357 </field>
358 <addr name="DMA_CMD5" addr="0x1b4"/> 358 <field>
359 <addr name="DMA_CMD6" addr="0x1d4"/> 359 <name>SCLKDIV</name>
360 <addr name="DMA_CMD7" addr="0x1f4"/> 360 <desc>System Clock Divisor</desc>
361 </reg> 361 <position>4</position>
362 </dev> 362 <width>2</width>
363 <dev name="DSP" long_name="Digital Signal Processor" desc="" version="1.0"> 363 </field>
364 <addr name="DSP" addr="0xb0050000"/> 364 <field>
365 <reg name="HDR" desc="HIP data registers"> 365 <name>CCLKDIV</name>
366 <addr name="HDR0" addr="0x0"/> 366 <desc>CPU Clock Divisor</desc>
367 <addr name="HDR1" addr="0x4"/> 367 <position>2</position>
368 <addr name="HDR2" addr="0x8"/> 368 <width>2</width>
369 <addr name="HDR3" addr="0xc"/> 369 </field>
370 <addr name="HDR4" addr="0x10"/> 370 <field>
371 <addr name="HDR5" addr="0x14"/> 371 <name>DCEN</name>
372 <addr name="HSR6" addr="0x18"/> 372 <desc>Core CLK DC Enable</desc>
373 <addr name="HSR7" addr="0x1c"/> 373 <position>1</position>
374 </reg> 374 </field>
375 <reg name="CTL" desc=""> 375 </register>
376 <addr name="CTL" addr="0x20"/> 376 </node>
377 </reg> 377 <node>
378 </dev> 378 <name>SDRCLK</name>
379 <dev name="GPIO" long_name="" desc="" version="1.0"> 379 <instance>
380 <addr name="GPIO" addr="0xb01c0000"/> 380 <name>SDRCLK</name>
381 <reg name="OUTEN" desc=""> 381 <address>0x10</address>
382 <addr name="AOUTEN" addr="0x0"/> 382 </instance>
383 <addr name="BOUTEN" addr="0xc"/> 383 <register>
384 </reg> 384 <desc>SDRAM Interface CLK Control Register</desc>
385 <reg name="INEN" desc=""> 385 <field>
386 <addr name="AINEN" addr="0x4"/> 386 <name>RESERVED31_2</name>
387 <addr name="BINEN" addr="0x10"/> 387 <position>2</position>
388 </reg> 388 <width>30</width>
389 <reg name="DAT" desc=""> 389 </field>
390 <addr name="ADAT" addr="0x8"/> 390 <field>
391 <addr name="BDAT" addr="0x14"/> 391 <name>SDRDIV</name>
392 </reg> 392 <position>0</position>
393 <reg name="MFCTL0" desc=""> 393 <width>2</width>
394 <addr name="MFCTL0" addr="0x18"/> 394 </field>
395 <field name="RESERVED31_25" desc="" bitrange="31:25"/> 395 </register>
396 <field name="GPIOA2_0" desc="" bitrange="24:22"> 396 </node>
397 <value name="NAND_CLE_RB_ALE" value="0x1" desc=""/> 397 <node>
398 <value name="LCD_RS_WD9_WD0" value="0x2" desc=""/> 398 <name>NANDCLK</name>
399 <value name="SD_CMD" value="0x4" desc=""/> 399 <instance>
400 </field> 400 <name>NANDCLK</name>
401 <field name="CEB6" desc="" bitrange="21:20"> 401 <address>0x18</address>
402 <value name="LCD_CE" value="0x2" desc=""/> 402 </instance>
403 <value name="SD_CLK" value="0x3" desc=""/> 403 <register>
404 </field> 404 <desc>NAND Interface CLK Control Register</desc>
405 <field name="RESERVED19_16" desc="" bitrange="19:16"/> 405 <field>
406 <field name="CEB3" desc="" bitrange="15:14"> 406 <name>RESERVED31_4</name>
407 <value name="NAND_CEB3" value="0x1" desc=""/> 407 <position>4</position>
408 <value name="LCD_CE" value="0x2" desc=""/> 408 <width>28</width>
409 </field> 409 </field>
410 <field name="CEB2" desc="" bitrange="13:12"> 410 <field>
411 <value name="NAND_CEB2" value="0x1" desc=""/> 411 <name>NANDDIV</name>
412 <value name="LCD_CE" value="0x2" desc=""/> 412 <position>0</position>
413 </field> 413 <width>4</width>
414 <field name="CEB1" desc="" bitrange="11:10"> 414 </field>
415 <value name="NAND_CEB1" value="0x1" desc=""/> 415 </register>
416 <value name="LCD_CE" value="0x2" desc=""/> 416 </node>
417 </field> 417 <node>
418 <field name="CEB0" desc="" bitrange="9:8"> 418 <name>SDCLK</name>
419 <value name="NAND_CEB0" value="0x1" desc=""/> 419 <instance>
420 <value name="LCD_CE" value="0x2" desc=""/> 420 <name>SDCLK</name>
421 </field> 421 <address>0x1c</address>
422 <field name="WRRD" desc="" bitrange="7:6"> 422 </instance>
423 <value name="NAND_WR_RD" value="0x1" desc=""/> 423 <register>
424 <value name="LCD_WRB_RDB" value="0x2" desc=""/> 424 <desc>SD Interface CLK Control Register
425 </field> 425</desc>
426 <field name="NAND_D7_0" desc="" bitrange="5:3"> 426 <field>
427 <value name="NAND_D7_0" value="0x1" desc=""/> 427 <name>RESERVED31_6</name>
428 <value name="LCD_WD17_10" value="0x2" desc=""/> 428 <position>6</position>
429 </field> 429 <width>26</width>
430 <field name="NAND_D15_8" desc="" bitrange="2:0"> 430 </field>
431 <value name="NAND_D15_8" value="0x1" desc=""/> 431 <field>
432 <value name="LCD_WD8_1" value="0x2" desc=""/> 432 <name>CKEN</name>
433 <value name="SDR_D7_0" value="0x4" desc=""/> 433 <desc>SD Interface Clock Enable</desc>
434 </field> 434 <position>5</position>
435 </reg> 435 </field>
436 <reg name="MFCTL1" desc=""> 436 <field>
437 <addr name="MFCTL1" addr="0x1c"/> 437 <name>D128</name>
438 <field name="MFEN" desc="" bitrange="31:31"/> 438 <desc>Enable Divide 128 circuit</desc>
439 <field name="RESERVED30_18" desc="" bitrange="30:18"/> 439 <position>4</position>
440 <field name="SD2E" desc="" bitrange="17:17"/> 440 </field>
441 <field name="RBS" desc="" bitrange="16:16"/> 441 <field>
442 <field name="RESERVED15_12" desc="" bitrange="15:12"/> 442 <name>SDDIV</name>
443 <field name="SIR0" desc="" bitrange="11:11"/> 443 <position>0</position>
444 <field name="SPTR" desc="" bitrange="10:9"> 444 <width>4</width>
445 <value name="I2C1_SCL_ADA" value="0x1" desc=""/> 445 </field>
446 <value name="UART2_TX_RX" value="0x2" desc=""/> 446 </register>
447 </field> 447 </node>
448 <field name="U2TR" desc="" bitrange="8:8"> 448 <node>
449 <value name="UART2_TX_RX" value="0x0" desc=""/> 449 <name>MHACLK</name>
450 <value name="I2C2_SCL_SDA" value="0x1" desc=""/> 450 <instance>
451 </field> 451 <name>MHACLK</name>
452 <field name="RESERVED7_6" desc="" bitrange="7:6"/> 452 <address>0x20</address>
453 <field name="I2C1SS" desc="" bitrange="5:4"> 453 </instance>
454 <value name="I2C1_SCL_SDA" value="0x0" desc=""/> 454 <register>
455 <value name="UART2_TX_RX" value="0x1" desc=""/> 455 <desc>MHA CLK Control Register</desc>
456 </field> 456 <field>
457 <field name="RESERVED3_0" desc="" bitrange="3:0"/> 457 <name>RESERVED31_4</name>
458 </reg> 458 <position>4</position>
459 </dev> 459 <width>28</width>
460 <dev name="I2C" long_name="" desc="" version="1.0"> 460 </field>
461 <addr name="I2C1" addr="0xb0180000"/> 461 <field>
462 <addr name="I2C2" addr="0xb0180020"/> 462 <name>MHADIV</name>
463 <reg name="CTL" desc=""> 463 <position>0</position>
464 <addr name="CTL" addr="0x0"/> 464 <width>4</width>
465 <field name="RESERVED31_9" desc="" bitrange="31:9"/> 465 </field>
466 <field name="PUEN" desc="nternal Pull-up Resistor (4.7k) Enable" bitrange="8:8"/> 466 </register>
467 <field name="EN" desc="Block enable" bitrange="7:7"/> 467 </node>
468 <field name="SIE" desc="START Condition Generates IRQ Enable (only for slave mode)" bitrange="6:6"/> 468 <node>
469 <field name="IRQE" desc="IRQ Enable" bitrange="5:5"/> 469 <name>UART2CLK</name>
470 <field name="MS" desc="Mode select" bitrange="4:4"> 470 <instance>
471 <value name="MASTER" value="0x0" desc=""/> 471 <name>UART2CLK</name>
472 <value name="SLAVE" value="0x1" desc=""/> 472 <address>0x2c</address>
473 </field> 473 </instance>
474 <field name="GBCC" desc="Generating Bus Control Condition (only for master mode)" bitrange="3:2"> 474 <register>
475 <value name="NOP" value="0x0" desc=""/> 475 <desc>Uart2 CLK Control Register</desc>
476 <value name="START" value="0x1" desc=""/> 476 <field>
477 <value name="STOP" value="0x2" desc=""/> 477 <name>RESERVED31_17</name>
478 <value name="REPEATED_START" value="0x3" desc=""/> 478 <position>17</position>
479 </field> 479 <width>15</width>
480 <field name="RB" desc="Release Bus. Writing 1 to this bit will release the clock and data line to idle. MCU should write 1 to this bit after transmitting or receiving the last bit of&#10;the whole transfer.&#10;" bitrange="1:1"/> 480 </field>
481 <field name="GRAS" desc="Generating/Receiving Acknowledge Signal" bitrange="0:0"/> 481 <field>
482 </reg> 482 <name>U2EN</name>
483 <reg name="CLKDIV" desc=""> 483 <desc>Uart2 Clock Enable
484 <addr name="CLKDIV" addr="0x4"/> 484</desc>
485 <field name="RESERVED31_8" desc="" bitrange="31:8"/> 485 <position>16</position>
486 <field name="CLKDIV" desc="Clock Divider Factor (only for master mode). I2Cx clock (SCL) can select standard (100kbps) mode and fast (400kbps) mode. Calculating SCL is as follows: SCL=PCLK/(CLKDIV*16)&#10;" bitrange="7:0"/> 486 </field>
487 </reg> 487 <field>
488 <reg name="STAT" desc=""> 488 <name>UART2DIV</name>
489 <addr name="STAT" addr="0x8"/> 489 <position>0</position>
490 <field name="RESERVED31_8" desc="" bitrange="31:8"/> 490 <width>16</width>
491 <field name="TRC" desc="Transmit/Receive Complete Bit" bitrange="7:7"/> 491 </field>
492 <field name="STPD" desc="STOP Detect Bit " bitrange="6:6"/> 492 </register>
493 <field name="STAD" desc="START Detect Bit" bitrange="5:5"/> 493 </node>
494 <field name="RWST" desc="Read/Write Status Bit (only for Slave mode)" bitrange="4:4"/> 494 <node>
495 <field name="LBST" desc="Last Byte Status Bit" bitrange="3:3"/> 495 <name>DMACLK</name>
496 <field name="IRQP" desc="IRQ Pending Bit" bitrange="2:2"/> 496 <instance>
497 <field name="OVST" desc="Overflow Status Bit" bitrange="1:1"/> 497 <name>DMACLK</name>
498 <field name="WCO" desc="Writing Collision Bit" bitrange="0:0"/> 498 <address>0x30</address>
499 </reg> 499 </instance>
500 <reg name="ADDR" desc=""> 500 <register>
501 <addr name="ADDR" addr="0xc"/> 501 <desc>DMA CLK Control Register</desc>
502 <field name="RESERVED31_8" desc="" bitrange="31:8"/> 502 <field>
503 <field name="SDAD" desc="Slave Device Address" bitrange="7:1"/> 503 <name>RESERVED31_4</name>
504 <field name="RWCM" desc="Read/Write Control or Match" bitrange="0:0"/> 504 <position>4</position>
505 </reg> 505 <width>28</width>
506 <reg name="DAT" desc=""> 506 </field>
507 <addr name="DAT" addr="0x10"/> 507 <field>
508 <field name="RESERVED31_8" desc="" bitrange="31:8"/> 508 <name>D7EN</name>
509 <field name="TXRXDAT" desc="Transmit/Receive Data" bitrange="7:0"/> 509 <desc>DMA 7 (Special Channel) Clock Enable</desc>
510 </reg> 510 <position>3</position>
511 </dev> 511 </field>
512 <dev name="INTC" long_name="Interrupt Controller" desc="" version="1.0"> 512 <field>
513 <addr name="INTC" addr="0xb0020000"/> 513 <name>D6EN</name>
514 <reg name="PD" desc=""> 514 <desc>DMA 6 (Special Channel) Clock Enable</desc>
515 <addr name="PD" addr="0x0"/> 515 <position>2</position>
516 </reg> 516 </field>
517 <reg name="MSK" desc=""> 517 <field>
518 <addr name="MSK" addr="0x4"/> 518 <name>D5EN</name>
519 </reg> 519 <desc>DMA 5 (Special Channel) Clock Enable</desc>
520 <reg name="CFG" desc=""> 520 <position>1</position>
521 <addr name="CFG0" addr="0x8"/> 521 </field>
522 <addr name="CFG1" addr="0xc"/> 522 <field>
523 <addr name="CFG2" addr="0x10"/> 523 <name>D4EN</name>
524 </reg> 524 <desc>DMA 4 (Special Channel) Clock Enable</desc>
525 <reg name="EXTCTL" desc=""> 525 <position>0</position>
526 <addr name="EXTCTL" addr="0x14"/> 526 </field>
527 </reg> 527 </register>
528 </dev> 528 </node>
529 <dev name="IR" long_name="" desc="" version="1.0"> 529 <node>
530 <addr name="IR" addr="0xb0160010"/> 530 <name>FMCLK</name>
531 </dev> 531 <instance>
532 <dev name="KEY" long_name="" desc="" version="1.0"> 532 <name>FMCLK</name>
533 <addr name="KEY" addr="0xb01a0000"/> 533 <address>0x34</address>
534 </dev> 534 </instance>
535 <dev name="MCA" long_name="Motion Compensation Accelerator" desc="" version="1.0"> 535 <register>
536 <addr name="MCA" addr="0xb0080000"/> 536 <desc>FM CLK Control Register</desc>
537 <reg name="CTL" desc=""> 537 <field>
538 <addr name="CTL" addr="0x0"/> 538 <name>RESERVED31_6</name>
539 </reg> 539 <position>6</position>
540 </dev> 540 <width>26</width>
541 <dev name="MHA" long_name="Media Hardware Accelerator" desc="" version="1.0"> 541 </field>
542 <addr name="MHA" addr="0xb00c0000"/> 542 <field>
543 <reg name="CTL" desc=""> 543 <name>BCKE</name>
544 <addr name="CTL" addr="0x0"/> 544 <desc>PWM Back Light clock Enable</desc>
545 </reg> 545 <position>5</position>
546 <reg name="CFG" desc=""> 546 </field>
547 <addr name="CFG" addr="0x4"/> 547 <field>
548 </reg> 548 <name>BCKS</name>
549 <reg name="DCSCLx" desc=""> 549 <desc>Back Light CLK source select</desc>
550 <addr name="DCSCL0" addr="0x10"/> 550 <position>4</position>
551 <addr name="DCSCL1" addr="0x14"/> 551 </field>
552 <addr name="DCSCL2" addr="0x18"/> 552 <field>
553 <addr name="DCSCL3" addr="0x1c"/> 553 <name>BCKCON</name>
554 </reg> 554 <desc>Divided PWM Back Light Special Clock Control</desc>
555 <reg name="QSCL" desc=""> 555 <position>2</position>
556 <addr name="QSCL" addr="0x20"/> 556 <width>2</width>
557 </reg> 557 </field>
558 </dev> 558 <field>
559 <dev name="NAND" long_name="NAND Flash Interface" desc="" version="1.0"> 559 <name>CLKS</name>
560 <addr name="NAND" addr="0xb00a0000"/> 560 <desc>FM Clock Output Selection</desc>
561 <reg name="CTL" desc=""> 561 <position>1</position>
562 <addr name="CTL" addr="0x0"/> 562 </field>
563 </reg> 563 <field>
564 <reg name="STATUS" desc=""> 564 <name>OUTE</name>
565 <addr name="STATUS" addr="0x4"/> 565 <desc>FM Clock Output Enable (From Test Pin)</desc>
566 </reg> 566 <position>0</position>
567 <reg name="FIFOTIM" desc=""> 567 </field>
568 <addr name="FIFOTIM" addr="0x8"/> 568 </register>
569 </reg> 569 </node>
570 <reg name="CLKCTL" desc=""> 570 <node>
571 <addr name="CLKCTL" addr="0xc"/> 571 <name>MCACLK</name>
572 </reg> 572 <instance>
573 <reg name="BYTECNT" desc=""> 573 <name>MCACLK</name>
574 <addr name="BYTECNT" addr="0x10"/> 574 <address>0x38</address>
575 </reg> 575 </instance>
576 <reg name="ADDR01" desc=""> 576 <register>
577 <addr name="ADDR01" addr="0x14"/> 577 <desc>MCA CLK Control Register</desc>
578 </reg> 578 <field>
579 <reg name="ADDR23" desc=""> 579 <name>RESERVED31_4</name>
580 <addr name="ADDR23" addr="0x18"/> 580 <position>4</position>
581 </reg> 581 <width>28</width>
582 <reg name="ADDR45" desc=""> 582 </field>
583 <addr name="ADDR45" addr="0x1c"/> 583 <field>
584 </reg> 584 <name>MCADIV</name>
585 <reg name="ADDR67" desc=""> 585 <position>0</position>
586 <addr name="ADDR67" addr="0x20"/> 586 <width>4</width>
587 </reg> 587 </field>
588 <reg name="BUF" desc=""> 588 </register>
589 <addr name="BUF0" addr="0x24"/> 589 </node>
590 <addr name="BUF1" addr="0x28"/> 590 <node>
591 </reg> 591 <name>DEVCLKEN</name>
592 <reg name="CMD" desc=""> 592 <instance>
593 <addr name="CMD" addr="0x2c"/> 593 <name>DEVCLKEN</name>
594 </reg> 594 <address>0x80</address>
595 <reg name="ECCCTL" desc=""> 595 </instance>
596 <addr name="ECCCTL" addr="0x30"/> 596 <register>
597 </reg> 597 <desc>Device CLK Control Register</desc>
598 <reg name="HAMECC" desc=""> 598 <field>
599 <addr name="HAMECC0" addr="0x34"/> 599 <name>RESERVED31_27</name>
600 <addr name="HAMECC1" addr="0x38"/> 600 <position>27</position>
601 <addr name="HAMECC2" addr="0x3c"/> 601 <width>5</width>
602 </reg> 602 </field>
603 <reg name="HAMCEC" desc=""> 603 <field>
604 <addr name="HAMCEC" addr="0x40"/> 604 <name>GPIO</name>
605 </reg> 605 <position>26</position>
606 <reg name="RSE" desc=""> 606 </field>
607 <addr name="RSE0" addr="0x44"/> 607 <field>
608 <addr name="RSE1" addr="0x48"/> 608 <name>KEY</name>
609 <addr name="RSE2" addr="0x4c"/> 609 <position>25</position>
610 <addr name="RSE3" addr="0x50"/> 610 </field>
611 </reg> 611 <field>
612 <reg name="RSPS" desc=""> 612 <name>RESERVED24</name>
613 <addr name="RSPS0" addr="0x54"/> 613 <position>24</position>
614 <addr name="RSPS1" addr="0x58"/> 614 </field>
615 <addr name="RSPS2" addr="0x5c"/> 615 <field>
616 </reg> 616 <name>I2C</name>
617 <reg name="FIFODATA" desc=""> 617 <position>23</position>
618 <addr name="FIFODATA" addr="0x60"/> 618 </field>
619 </reg> 619 <field>
620 <reg name="DEBUG" desc=""> 620 <name>UART</name>
621 <addr name="DEBUG" addr="0x70"/> 621 <position>22</position>
622 </reg> 622 </field>
623 </dev> 623 <field>
624 <dev name="PCM" long_name="" desc="" version="1.0"> 624 <name>RESERVED21_19</name>
625 <addr name="PCM" addr="0xb0150000"/> 625 <position>19</position>
626 </dev> 626 <width>3</width>
627 <dev name="PCNT" long_name="Performance Counters" desc="The base address is not clear!" version="1.0"> 627 </field>
628 <addr name="PCNT" addr="0xb003c000"/> 628 <field>
629 <reg name="CTL" desc=""> 629 <name>ADC</name>
630 <addr name="CTL" addr="0x0"/> 630 <position>18</position>
631 </reg> 631 </field>
632 <reg name="PCx" desc=""> 632 <field>
633 <addr name="PC0" addr="0x4"/> 633 <name>DAC</name>
634 <addr name="PC1" addr="0x8"/> 634 <position>17</position>
635 </reg> 635 </field>
636 </dev> 636 <field>
637 <dev name="PMU" long_name="Power Management Unit" desc="" version="1.0"> 637 <name>DSPC</name>
638 <addr name="PMU" addr="0xb0000000"/> 638 <position>16</position>
639 <reg name="CTL" desc=""> 639 </field>
640 <addr name="CTL" addr="0x0"/> 640 <field>
641 <field name="LBRM" desc="" bitrange="31:31"/> 641 <name>MCA</name>
642 <field name="VCVS" desc="" bitrange="30:28"/> 642 <position>15</position>
643 <field name="LBNM" desc="" bitrange="27:27"/> 643 </field>
644 <field name="VDVS" desc="" bitrange="26:24"/> 644 <field>
645 <field name="VCDE" desc="" bitrange="23:23"/> 645 <name>MHA</name>
646 <field name="VCVD" desc="" bitrange="22:20"/> 646 <position>14</position>
647 <field name="VDDE" desc="" bitrange="19:19"/> 647 </field>
648 <field name="VDVD" desc="" bitrange="18:16"/> 648 <field>
649 <field name="BLEN" desc="" bitrange="15:15"/> 649 <name>USBC</name>
650 <field name="VCOE" desc="" bitrange="14:14"/> 650 <position>13</position>
651 <field name="LA6E" desc="" bitrange="13:13"/> 651 </field>
652 <field name="LA4E" desc="" bitrange="12:12"/> 652 <field>
653 <field name="IBIAS" desc="" bitrange="11:10"/> 653 <name>RESERVED12</name>
654 <field name="OSCFREQ" desc="" bitrange="9:8"/> 654 <position>12</position>
655 <field name="DC1M" desc="" bitrange="7:7"/> 655 </field>
656 <field name="DC2M" desc="" bitrange="6:6"/> 656 <field>
657 <field name="BLVS" desc="" bitrange="5:3"/> 657 <name>SD</name>
658 <field name="VDV0" desc="" bitrange="2:2"/> 658 <position>11</position>
659 <field name="PWRM" desc="" bitrange="1:0"/> 659 </field>
660 </reg> 660 <field>
661 <reg name="LRADC" desc=""> 661 <name>RESERVED10</name>
662 <addr name="LRADC" addr="0x4"/> 662 <position>10</position>
663 <field name="RESERVED31_28" desc="" bitrange="31:28"/> 663 </field>
664 <field name="REMOADC4" desc="" bitrange="27:24"/> 664 <field>
665 <field name="RESERVED23_20" desc="" bitrange="23:22"/> 665 <name>NAND</name>
666 <field name="BATADC6" desc="" bitrange="21:16"/> 666 <position>9</position>
667 <field name="RESERVED15_14" desc="" bitrange="15:14"/> 667 </field>
668 <field name="TEMPADC6" desc="" bitrange="13:8"/> 668 <field>
669 <field name="RESERVED7_0" desc="" bitrange="7:0"/> 669 <name>DMAC</name>
670 </reg> 670 <position>8</position>
671 <reg name="CHG" desc=""> 671 </field>
672 <addr name="CHG" addr="0x8"/> 672 <field>
673 <field name="EN" desc="" bitrange="31:31"/> 673 <name>PCNT</name>
674 <field name="CURRENT" desc="" bitrange="30:28"> 674 <position>7</position>
675 <value name="CURRENT_50mA" value="0x0" desc=""/> 675 </field>
676 <value name="CURRENT_100mA" value="0x1" desc=""/> 676 <field>
677 <value name="CURRENT_150mA" value="0x2" desc=""/> 677 <name>SDRM</name>
678 <value name="CURRENT_200mA" value="0x3" desc=""/> 678 <position>6</position>
679 <value name="CURRENT_250mA" value="0x4" desc=""/> 679 </field>
680 <value name="CURRENT_300mA" value="0x5" desc=""/> 680 <field>
681 <value name="CURRENT_400mA" value="0x6" desc=""/> 681 <name>SDRC</name>
682 <value name="CURRENT_500mA" value="0x7" desc=""/> 682 <position>5</position>
683 </field> 683 </field>
684 <field name="STAT" desc="" bitrange="27:27"> 684 <field>
685 <value name="DISCHARGING" value="0x0" desc=""/> 685 <name>DSPM</name>
686 <value name="CHARGING" value="0x1" desc=""/> 686 <position>4</position>
687 </field> 687 </field>
688 <field name="CHGPHASE" desc="" bitrange="26:25"> 688 <field>
689 <value name="RESERVED" value="0x0" desc=""/> 689 <name>RESERVED3</name>
690 <value name="PRECHARGE" value="0x1" desc=""/> 690 <position>3</position>
691 <value name="CC" value="0x2" desc=""/> 691 </field>
692 <value name="CV" value="0x3" desc=""/> 692 <field>
693 </field> 693 <name>RMOC</name>
694 <field name="RESERVED24_16" desc="" bitrange="24:16"/> 694 <position>2</position>
695 <field name="PBLS" desc="" bitrange="15:15"/> 695 </field>
696 <field name="PPHS" desc="" bitrange="14:14"/> 696 <field>
697 <field name="RESERVED13" desc="" bitrange="13:13"/> 697 <name>YUV</name>
698 <field name="PDUT" desc="" bitrange="12:8"/> 698 <position>1</position>
699 <field name="RESERVED7" desc="" bitrange="7:7"/> 699 </field>
700 <field name="BLV0" desc="" bitrange="6:6"/> 700 <field>
701 <field name="TMPSET" desc="" bitrange="5:4"> 701 <name>RESERVED0</name>
702 <value name="TEMP_40C" value="0x0" desc=""/> 702 <position>0</position>
703 <value name="TEMP_45C" value="0x1" desc=""/> 703 </field>
704 <value name="TEMP_50C" value="0x2" desc=""/> 704 </register>
705 <value name="TEMP_55C" value="0x3" desc=""/> 705 </node>
706 </field> 706 <node>
707 <field name="LBNMIVS" desc="" bitrange="3:2"> 707 <name>DEVRST</name>
708 <value name="VOLTAGE_2_9" value="0x0" desc=""/> 708 <instance>
709 <value name="VOLTAGE_3_1" value="0x1" desc=""/> 709 <name>DEVRST</name>
710 <value name="VOLTAGE_3_3" value="0x2" desc=""/> 710 <address>0x84</address>
711 <value name="VOLTAGE_3_5" value="0x3" desc=""/> 711 </instance>
712 </field> 712 <register>
713 <field name="LBRVS" desc="" bitrange="1:0"> 713 <desc>Device Reset Control Register</desc>
714 <value name="VOLTAGE_2_7" value="0x0" desc=""/> 714 <field>
715 <value name="VOLTAGE_2_9" value="0x1" desc=""/> 715 <name>RESERVED31</name>
716 <value name="VOLTAGE_3_1" value="0x2" desc=""/> 716 <position>31</position>
717 <value name="VOLTAGE_3_3" value="0x3" desc=""/> 717 </field>
718 </field> 718 <field>
719 </reg> 719 <name>GPIO</name>
720 </dev> 720 <position>30</position>
721 <dev name="RTCWDT" long_name="Real Time Clock, Timers and Watchdog" desc="" version="1.0"> 721 </field>
722 <addr name="RTC" addr="0xb0018000"/> 722 <field>
723 <reg name="CTL" desc=""> 723 <name>KEY</name>
724 <addr name="CTL" addr="0x0"/> 724 <position>29</position>
725 </reg> 725 </field>
726 <reg name="DHMS" desc=""> 726 <field>
727 <addr name="DHMS" addr="0x4"/> 727 <name>RESERVED28</name>
728 <field name="RESERVED31_27" desc="" bitrange="31:27"/> 728 <position>28</position>
729 <field name="DAY" desc="" bitrange="26:24"/> 729 </field>
730 <field name="RESERVED23_21" desc="" bitrange="23:21"/> 730 <field>
731 <field name="HOUR" desc="" bitrange="20:16"/> 731 <name>I2C</name>
732 <field name="RESERVED15_14" desc="" bitrange="15:14"/> 732 <position>27</position>
733 <field name="MIN" desc="" bitrange="13:8"/> 733 </field>
734 <field name="RESERVED7_6" desc="" bitrange="7:6"/> 734 <field>
735 <field name="SEC" desc="" bitrange="5:0"/> 735 <name>UART</name>
736 </reg> 736 <position>26</position>
737 <reg name="YMD" desc=""> 737 </field>
738 <addr name="YMD" addr="0x8"/> 738 <field>
739 <field name="RESERVED31" desc="" bitrange="31:31"/> 739 <name>RESERVED25_23</name>
740 <field name="CENT" desc="" bitrange="30:24"/> 740 <position>23</position>
741 <field name="RESERVED23" desc="" bitrange="23:23"/> 741 <width>3</width>
742 <field name="YEAR" desc="" bitrange="22:16"/> 742 </field>
743 <field name="RESERVED15_12" desc="" bitrange="15:12"/> 743 <field>
744 <field name="MON" desc="" bitrange="11:8"/> 744 <name>ADC</name>
745 <field name="RESERVED7_5" desc="" bitrange="7:5"/> 745 <position>22</position>
746 <field name="DATE" desc="" bitrange="4:0"/> 746 </field>
747 </reg> 747 <field>
748 <reg name="DHMSALM" desc=""> 748 <name>DAC</name>
749 <addr name="DHMSALM" addr="0xc"/> 749 <position>21</position>
750 <field name="RESERVED31_21" desc="" bitrange="31:21"/> 750 </field>
751 <field name="HOURAL" desc="" bitrange="20:16"/> 751 <field>
752 <field name="RESERVED15_14" desc="" bitrange="15:14"/> 752 <name>DSPC</name>
753 <field name="MINAL" desc="" bitrange="13:8"/> 753 <desc>DSP control block reset</desc>
754 <field name="RESERVED7_6" desc="" bitrange="7:6"/> 754 <position>20</position>
755 <field name="SECAL" desc="" bitrange="5:0"/> 755 </field>
756 </reg> 756 <field>
757 <reg name="YMDALM" desc=""> 757 <name>INTC</name>
758 <addr name="YMDALM" addr="0x10"/> 758 <position>19</position>
759 <field name="RESERVED31_23" desc="" bitrange="31:23"/> 759 </field>
760 <field name="YEARAL" desc="" bitrange="22:16"/> 760 <field>
761 <field name="RESERVED15_12" desc="" bitrange="15:12"/> 761 <name>RTC</name>
762 <field name="MONAL" desc="" bitrange="11:8"/> 762 <position>18</position>
763 <field name="RESERVED7_5" desc="" bitrange="7:5"/> 763 </field>
764 <field name="DATEAL" desc="" bitrange="4:0"/> 764 <field>
765 </reg> 765 <name>PMU</name>
766 <reg name="WDCTL" desc=""> 766 <position>17</position>
767 <addr name="WDCTL" addr="0x14"/> 767 </field>
768 </reg> 768 <field>
769 <reg name="TxCTL" desc=""> 769 <name>RESERVED16_14</name>
770 <addr name="T0CTL" addr="0x18"/> 770 <position>14</position>
771 <addr name="T1CTL" addr="0x20"/> 771 <width>3</width>
772 </reg> 772 </field>
773 <reg name="Tx" desc=""> 773 <field>
774 <addr name="T0" addr="0x1c"/> 774 <name>DSPM</name>
775 <addr name="T1" addr="0x24"/> 775 <desc>SRAM DSP MEM reset</desc>
776 </reg> 776 <position>13</position>
777 </dev> 777 </field>
778 <dev name="SD" long_name="SD/MMC Interface" desc="" version=""> 778 <field>
779 <addr name="SD" addr="0xb00b0000"/> 779 <name>TVENC</name>
780 <reg name="CTL" desc=""> 780 <position>12</position>
781 <addr name="CTL" addr="0x0"/> 781 </field>
782 </reg> 782 <field>
783 <reg name="CMDRSP" desc=""> 783 <name>YUV</name>
784 <addr name="CMDRSP" addr="0x4"/> 784 <position>11</position>
785 </reg> 785 </field>
786 <reg name="RW" desc=""> 786 <field>
787 <addr name="RW" addr="0x8"/> 787 <name>MCA</name>
788 </reg> 788 <position>10</position>
789 <reg name="FIFOCTL" desc=""> 789 </field>
790 <addr name="FIFOCTL" addr="0xc"/> 790 <field>
791 </reg> 791 <name>USB</name>
792 <reg name="CMD" desc=""> 792 <position>9</position>
793 <addr name="CMD" addr="0x10"/> 793 </field>
794 </reg> 794 <field>
795 <reg name="ARG" desc=""> 795 <name>RESERVED8</name>
796 <addr name="ARG" addr="0x14"/> 796 <position>8</position>
797 </reg> 797 </field>
798 <reg name="CRC7" desc=""> 798 <field>
799 <addr name="CRC7" addr="0x18"/> 799 <name>MHA</name>
800 </reg> 800 <position>7</position>
801 <reg name="RSPBUFx" desc=""> 801 </field>
802 <addr name="RSPBUF0" addr="0x1c"/> 802 <field>
803 <addr name="RSPBUF1" addr="0x20"/> 803 <name>SD</name>
804 <addr name="RSPBUF2" addr="0x24"/> 804 <position>6</position>
805 <addr name="RSPBUF3" addr="0x28"/> 805 </field>
806 <addr name="RSPBUF4" addr="0x2c"/> 806 <field>
807 </reg> 807 <name>NAND</name>
808 <reg name="DAT" desc=""> 808 <position>5</position>
809 <addr name="DAT" addr="0x30"/> 809 </field>
810 </reg> 810 <field>
811 <reg name="CLK" desc=""> 811 <name>RESERVED4</name>
812 <addr name="CLK" addr="0x34"/> 812 <position>4</position>
813 </reg> 813 </field>
814 <reg name="BYTECNT" desc=""> 814 <field>
815 <addr name="BYTECNT" addr="0x38"/> 815 <name>DMAC</name>
816 </reg> 816 <position>3</position>
817 </dev> 817 </field>
818 <dev name="SDR" long_name="SDRAM Interface" desc="" version="1.0"> 818 <field>
819 <addr name="SDR" addr="0xb0070000"/> 819 <name>PCNT</name>
820 <reg name="CTL" desc=""> 820 <position>2</position>
821 <addr name="CTL" addr="0x0"/> 821 </field>
822 </reg> 822 <field>
823 <reg name="ADDRCFG" desc=""> 823 <name>RESERVED1</name>
824 <addr name="ADDRCFG" addr="0x4"/> 824 <position>1</position>
825 </reg> 825 </field>
826 <reg name="EN" desc=""> 826 <field>
827 <addr name="EN" addr="0x8"/> 827 <name>SDR</name>
828 <field name="RESERVED31_1" desc="" bitrange="31:1"/> 828 <desc>SDRAM Control register and SDRAM block Reset</desc>
829 <field name="EN" desc="" bitrange="0:0"/> 829 <position>0</position>
830 </reg> 830 </field>
831 <reg name="CMD" desc=""> 831 </register>
832 <addr name="CMD" addr="0xc"/> 832 </node>
833 </reg> 833 </node>
834 <reg name="STAT" desc=""> 834 <node>
835 <addr name="STAT" addr="0x10"/> 835 <name>DAC</name>
836 </reg> 836 <title>Digital Analog Converter</title>
837 <reg name="RFSH" desc=""> 837 <instance>
838 <addr name="RFSH" addr="0x14"/> 838 <name>DAC</name>
839 </reg> 839 <address>0xb0100000</address>
840 <reg name="MODE" desc=""> 840 </instance>
841 <addr name="MODE" addr="0x18"/> 841 </node>
842 </reg> 842 <node>
843 <reg name="MOBILE" desc=""> 843 <name>DMAC</name>
844 <addr name="MOBILE" addr="0x1c"/> 844 <title>Direct Memory Access Controller</title>
845 </reg> 845 <desc>Channels 0-3 work with retular AHB bus, channels 4-7 work with 'special' bus.</desc>
846 </dev> 846 <instance>
847 <dev name="SPDIF" long_name="Sony Philips Digital Interface" desc="" version="1.0"> 847 <name>DMAC</name>
848 <addr name="SPDIF" addr="0xb0140000"/> 848 <address>0xb0060000</address>
849 </dev> 849 </instance>
850 <dev name="SPI" long_name="" desc="" version="1.0"> 850 <node>
851 <addr name="SPI" addr="0xb0190000"/> 851 <name>CTL</name>
852 </dev> 852 <instance>
853 <dev name="SRAMOC" long_name="SRAM on Chip" desc="" version="1.0"> 853 <name>CTL</name>
854 <addr name="SRAMOC" addr="0xb0030000"/> 854 <address>0x0</address>
855 <reg name="CTL" desc=""> 855 </instance>
856 <addr name="CTL" addr="0x0"/> 856 <register/>
857 </reg> 857 </node>
858 <reg name="STAT" desc=""> 858 <node>
859 <addr name="STAT" addr="0x4"/> 859 <name>IRQEN</name>
860 </reg> 860 <instance>
861 </dev> 861 <name>IRQEN</name>
862 <dev name="TP" long_name="" desc="" version="1.0"> 862 <address>0x4</address>
863 <addr name="TP" addr="0xb0120000"/> 863 </instance>
864 </dev> 864 <register/>
865 <dev name="UART" long_name="" desc="" version="1.0"> 865 </node>
866 <addr name="UART0" addr="0xb0160000"/> 866 <node>
867 <addr name="UART1" addr="0xb0160020"/> 867 <name>IRQPD</name>
868 </dev> 868 <instance>
869 <dev name="UDC" long_name="Usb Device Controller" desc="CAST cusb2-otg IP core" version="1.0"> 869 <name>IRQPD</name>
870 <addr name="UDC" addr="0xb00e0000"/> 870 <address>0x8</address>
871 <reg name="EP0BC" desc="ep0 byte count register"> 871 </instance>
872 <addr name="OUT0BC" addr="0x0"/> 872 <register/>
873 <addr name="IN0BC" addr="0x1"/> 873 </node>
874 <field name="RESERVED" desc="" bitrange="31:8"/> 874 <node>
875 <field name="BC" desc="" bitrange="7:0"/> 875 <name>DMA_MODE</name>
876 </reg> 876 <instance>
877 <reg name="EP0CS" desc=""> 877 <name>DMA_MODE</name>
878 <addr name="EP0CS" addr="0x2"/> 878 <range>
879 <field name="RESERVED" desc="" bitrange="31:8"/> 879 <first>0</first>
880 <field name="OUT_BUSY" desc="" bitrange="3:3"/> 880 <count>8</count>
881 <field name="IN_BUSY" desc="" bitrange="2:2"/> 881 <base>0x100</base>
882 <field name="NAK" desc="Writing 1 clears" bitrange="1:1"/> 882 <stride>0x20</stride>
883 <field name="STALL" desc="" bitrange="0:0"/> 883 </range>
884 </reg> 884 </instance>
885 <reg name="BCL" desc="Endpoint byte count LSB register"> 885 <register>
886 <addr name="OUT1BCL" addr="0x8"/> 886 <field>
887 <addr name="IN1BCL" addr="0xc"/> 887 <name>DBURLEN</name>
888 <addr name="OUT2BCL" addr="0x10"/> 888 <desc>Destination burst length. If burst lenght is 4 or 8 DDIR must be 0, DFXA must be 0, DDSP must be 0, DCOL must be 0. Burst must not cross a 1kB address boundary.</desc>
889 <addr name="IN2BCL" addr="0x14"/> 889 <position>29</position>
890 </reg> 890 <width>3</width>
891 <reg name="BCH" desc="Endpoint byte count MSB"> 891 <enum>
892 <addr name="OUT1BCH" addr="0x9"/> 892 <name>SINGLE</name>
893 <addr name="IN1BCH" addr="0xd"/> 893 <value>0x0</value>
894 <addr name="OUT2BCH" addr="0x11"/> 894 </enum>
895 <addr name="IN2BCH" addr="0x15"/> 895 <enum>
896 </reg> 896 <name>INCR4</name>
897 <reg name="CON" desc="Endpoint configuration register"> 897 <value>0x3</value>
898 <addr name="OUT1CON" addr="0xa"/> 898 </enum>
899 <addr name="IN1CON" addr="0xe"/> 899 <enum>
900 <addr name="OUT2CON" addr="0x12"/> 900 <name>INCR8</name>
901 <addr name="IN2CON" addr="0x16"/> 901 <value>0x5</value>
902 <field name="EP_ENABLE" desc="" bitrange="7:7"/> 902 </enum>
903 <field name="STALL" desc="" bitrange="6:6"/> 903 </field>
904 <field name="EP_TYPE" desc="" bitrange="3:2"> 904 <field>
905 <value name="RESERVED" value="0x0" desc=""/> 905 <name>RELO</name>
906 <value name="ISOCHRONOUS" value="0x1" desc=""/> 906 <desc>DMA Reload Bit.</desc>
907 <value name="BULK" value="0x2" desc=""/> 907 <position>28</position>
908 <value name="INTERRUPT" value="0x3" desc=""/> 908 </field>
909 </field> 909 <field>
910 <field name="SUBFIFOS" desc="" bitrange="1:0"> 910 <name>DDSP</name>
911 <value name="SINGLE" value="0x0" desc=""/> 911 <desc>Destination DSP mode.
912 <value name="DOUBLE" value="0x1" desc=""/> 912</desc>
913 <value name="TRIPLE" value="0x2" desc=""/> 913 <position>27</position>
914 <value name="QUAD" value="0x3" desc=""/> 914 </field>
915 </field> 915 <field>
916 </reg> 916 <name>DCOL</name>
917 <reg name="CS" desc="Endpoint status register"> 917 <desc>Destination Column Mode.</desc>
918 <addr name="OUT1CS" addr="0xb"/> 918 <position>26</position>
919 <addr name="IN1CS" addr="0xf"/> 919 </field>
920 <addr name="OUT2CS" addr="0x13"/> 920 <field>
921 <addr name="IN2CS" addr="0x17"/> 921 <name>DDIR</name>
922 <field name="AUTO" desc="" bitrange="4:4"/> 922 <desc>Destination address direction. If DBURLEN is INCR4 or INCR8 only INCREASE is allowed.</desc>
923 <field name="NPACK1" desc="" bitrange="3:3"/> 923 <position>25</position>
924 <field name="NPACK0" desc="" bitrange="2:2"/> 924 <enum>
925 <field name="BUSY" desc="" bitrange="1:1"/> 925 <name>INCREASE</name>
926 <field name="ERROR" desc="" bitrange="0:0"/> 926 <value>0x0</value>
927 </reg> 927 </enum>
928 <reg name="FIFODAT" desc="Endpoint FIFO"> 928 <enum>
929 <addr name="FIFO1DAT" addr="0x84"/> 929 <name>DECREASE</name>
930 <addr name="FIFO2DAT" addr="0x88"/> 930 <value>0x1</value>
931 </reg> 931 </enum>
932 <reg name="EP0DAT" desc="Endpoint 0 buffers each 64 bytes long."> 932 </field>
933 <addr name="EP0INDAT" addr="0x100"/> 933 <field>
934 <addr name="EP0OUTDAT" addr="0x140"/> 934 <name>DFXA</name>
935 </reg> 935 <desc>Destination Fixed Address bit.</desc>
936 <reg name="SETUPDAT" desc="SETUP packet buffer"> 936 <position>24</position>
937 <addr name="SETUPDAT" addr="0x180"/> 937 <enum>
938 </reg> 938 <name>NOT_FIXED</name>
939 <reg name="EPIRQ" desc="Endpoint irq flag register"> 939 <value>0x0</value>
940 <addr name="IN04IRQ" addr="0x188"/> 940 </enum>
941 <addr name="OUT04IRQ" addr="0x18a"/> 941 <enum>
942 <field name="EP_NUM" desc="" bitrange="2:0"/> 942 <name>FIXED</name>
943 </reg> 943 <value>0x1</value>
944 <reg name="USBIRQ" desc="General usb core irq flags"> 944 </enum>
945 <addr name="USBIRQ" addr="0x18c"/> 945 </field>
946 <field name="HS" desc="Enter high speed operation. Set by core on connection." bitrange="5:5"/> 946 <field>
947 <field name="RESET" desc="Asserted on usb reset." bitrange="4:4"/> 947 <name>DTRG</name>
948 <field name="SUSPEND" desc="" bitrange="3:3"/> 948 <desc>Destination DRQ Trig Source.</desc>
949 <field name="SETUP_TOKEN" desc="" bitrange="2:2"/> 949 <position>19</position>
950 <field name="SOF" desc="" bitrange="1:1"/> 950 <width>5</width>
951 <field name="SETUP_DATA" desc="Setup data are ready to be accessed in SETUPDAT buffer." bitrange="0:0"/> 951 <enum>
952 </reg> 952 <name>DAC</name>
953 <reg name="EPIEN" desc="Endpoint interrupt enable register"> 953 <value>0x6</value>
954 <addr name="IN04IEN" addr="0x194"/> 954 </enum>
955 <addr name="OUT04IEN" addr="0x196"/> 955 <enum>
956 <field name="EP_NUM" desc="" bitrange="2:0"/> 956 <name>SDRAM</name>
957 </reg> 957 <value>0x10</value>
958 <reg name="USBIEN" desc="General usb interrupts enable register"> 958 </enum>
959 <addr name="USBIEN" addr="0x198"/> 959 <enum>
960 <field name="HS" desc="" bitrange="5:5"/> 960 <name>IRAM</name>
961 <field name="RESET" desc="" bitrange="4:4"/> 961 <value>0x11</value>
962 <field name="SUSPEND" desc="" bitrange="3:3"/> 962 </enum>
963 <field name="SETUP_TOKEN" desc="" bitrange="2:2"/> 963 <enum>
964 <field name="SOF" desc="" bitrange="1:1"/> 964 <name>SD</name>
965 <field name="SETUP_DATA" desc="" bitrange="0:0"/> 965 <value>0x16</value>
966 </reg> 966 </enum>
967 <reg name="IVECT" desc="Interrupt vector register&#10;known (guessed) values:&#10;0x00 - SETUP&#10;0x10 - RESET&#10;0x14 - HS&#10;0x28 - EPs&#10;0xD8 - OTG"> 967 <enum>
968 <addr name="IVECT" addr="0x1a0"/> 968 <name>OTG</name>
969 </reg> 969 <value>0x17</value>
970 <reg name="ENDPRST" desc="Endpoint reset register"> 970 </enum>
971 <addr name="ENDPRST" addr="0x1a2"/> 971 <enum>
972 <field name="FIFO_RESET" desc="" bitrange="6:6"/> 972 <name>LCM</name>
973 <field name="TOGGLE_RESET" desc="" bitrange="5:5"/> 973 <value>0x18</value>
974 <field name="DIR" desc="" bitrange="4:4"> 974 </enum>
975 <value name="OUT" value="0x0" desc=""/> 975 </field>
976 <value name="IN" value="0x1" desc=""/> 976 <field>
977 </field> 977 <name>DTRANWID</name>
978 <field name="EP_NUM" desc="" bitrange="2:0"/> 978 <position>17</position>
979 </reg> 979 <width>2</width>
980 <reg name="USBCS" desc=""> 980 <enum>
981 <addr name="USBCS" addr="0x1a3"/> 981 <name>WIDTH8</name>
982 <field name="SOFT_CONNECT" desc="" bitrange="6:6"/> 982 <value>0x0</value>
983 <field name="SIGRESUME" desc="" bitrange="5:5"/> 983 </enum>
984 <field name="USBSPEED" desc="" bitrange="1:1"/> 984 <enum>
985 <field name="HCLSMODE" desc="" bitrange="0:0"/> 985 <name>WIDTH16</name>
986 </reg> 986 <value>0x1</value>
987 <reg name="FIFOCTRL" desc=""> 987 </enum>
988 <addr name="FIFOCTRL" addr="0x1a8"/> 988 <enum>
989 <field name="CPU_ACCESS" desc="" bitrange="7:7"/> 989 <name>WIDTH32</name>
990 <field name="DMA" desc="" bitrange="5:5"/> 990 <value>0x2</value>
991 <field name="DIR" desc="" bitrange="4:4"> 991 </enum>
992 <value name="OUT" value="0x0" desc=""/> 992 </field>
993 <value name="IN" value="0x1" desc=""/> 993 <field>
994 </field> 994 <name>DFXS</name>
995 <field name="EP_NUM" desc="" bitrange="2:0"/> 995 <desc>If DFXS=0, DMA will transfer in 8bit mode when remain counter is less than DTRANWID.
996 </reg> 996If DFXS=1, DMA will always transfer in DTRANWID.
997 <reg name="OTGIRQ" desc=""> 997</desc>
998 <addr name="OTGIRQ" addr="0x1bc"/> 998 <position>16</position>
999 <field name="PERIPH" desc="" bitrange="4:4"/> 999 </field>
1000 <field name="VBUSERR" desc="" bitrange="3:3"/> 1000 <field>
1001 <field name="LOCSOFT" desc="" bitrange="2:2"/> 1001 <name>SBURLEN</name>
1002 <field name="SPRDET" desc="" bitrange="1:1"/> 1002 <desc>Source burst length. If burst lenght is 4 or 8 DDIR must be 0, DFXA must be 0, DDSP must be 0, DCOL must be 0. Burst must not cross a 1kB address boundary.</desc>
1003 <field name="OTG_IDLE" desc="" bitrange="0:0"/> 1003 <position>13</position>
1004 </reg> 1004 <width>3</width>
1005 <reg name="OTGSTATUS" desc=""> 1005 <enum>
1006 <addr name="OTGSTATUS" addr="0x1bf"/> 1006 <name>SINGLE</name>
1007 </reg> 1007 <value>0x0</value>
1008 <reg name="OTGIEN" desc="OTG interrupt enable register"> 1008 </enum>
1009 <addr name="OTGIEN" addr="0x1c0"/> 1009 <enum>
1010 </reg> 1010 <name>INCR4</name>
1011 <reg name="HCMAXPCKL" desc="High speed max packed size LSB"> 1011 <value>0x3</value>
1012 <addr name="HCIN1MAXPCKL" addr="0x1e2"/> 1012 </enum>
1013 <addr name="HCOUT2MAXPCKL" addr="0x3e4"/> 1013 <enum>
1014 </reg> 1014 <name>INCR8</name>
1015 <reg name="STADDR" desc="Endpoint buffer start address"> 1015 <value>0x5</value>
1016 <addr name="OUT1STADDR" addr="0x304"/> 1016 </enum>
1017 <addr name="IN2STADDR" addr="0x348"/> 1017 </field>
1018 </reg> 1018 <field>
1019 <reg name="USBEIRQ" desc="USB extended irq register"> 1019 <name>SDSP</name>
1020 <addr name="USBEIRQ" addr="0x400"/> 1020 <desc>Source DSP mode.
1021 <field name="USB" desc="" bitrange="7:7"/> 1021</desc>
1022 <field name="WAKEUP" desc="" bitrange="6:6"/> 1022 <position>11</position>
1023 <field name="RESUME" desc="" bitrange="5:5"/> 1023 </field>
1024 <field name="CONDISCON" desc="" bitrange="4:4"/> 1024 <field>
1025 <field name="USBIEN" desc="" bitrange="3:3"/> 1025 <name>SCOL</name>
1026 <field name="WAKEUPIEN" desc="" bitrange="2:2"/> 1026 <desc>Source Column Mode.</desc>
1027 <field name="RESUMEIEN" desc="" bitrange="1:1"/> 1027 <position>10</position>
1028 <field name="CONDISCONIEN" desc="" bitrange="0:0"/> 1028 </field>
1029 </reg> 1029 <field>
1030 <reg name="USBERST" desc=""> 1030 <name>SDIR</name>
1031 <addr name="USBERST" addr="0x404"/> 1031 <desc>Source address direction. If SBURLEN is INCR4 or INCR8 only INCREASE is allowed.</desc>
1032 </reg> 1032 <position>9</position>
1033 <reg name="DMAEPSEL" desc=""> 1033 <enum>
1034 <addr name="DMAEPSEL" addr="0x40c"/> 1034 <name>INCREASE</name>
1035 <field name="EP_SEL" desc="" bitrange="31:0"> 1035 <value>0x0</value>
1036 <value name="UNKNOWN" value="0x0" desc=""/> 1036 </enum>
1037 <value name="EP1_IN" value="0x1" desc=""/> 1037 <enum>
1038 <value name="EP1_OUT" value="0x3" desc=""/> 1038 <name>DECREASE</name>
1039 <value name="EP2_IN" value="0x4" desc=""/> 1039 <value>0x1</value>
1040 <value name="EP2_OUT" value="0xc" desc=""/> 1040 </enum>
1041 </field> 1041 </field>
1042 </reg> 1042 <field>
1043 </dev> 1043 <name>SFXA</name>
1044 <dev name="YUV2RGB" long_name="Color Space Conversion Accelerator" desc="" version=""> 1044 <desc>Source Fixed Addres bit.</desc>
1045 <addr name="YUV2RGB" addr="0xb00f0000"/> 1045 <position>8</position>
1046 <reg name="CTL" desc=""> 1046 <enum>
1047 <addr name="CTL" addr="0x0"/> 1047 <name>NOT_FIXED</name>
1048 <field name="RESERVED" desc="" bitrange="31:22"/> 1048 <value>0x0</value>
1049 <field name="RFBM" desc="Read fifo block mode." bitrange="21:21"/> 1049 </enum>
1050 <field name="WFBM" desc="Write fifo block mode" bitrange="20:20"/> 1050 <enum>
1051 <field name="EN" desc="RGB Decoder enable." bitrange="19:19"/> 1051 <name>FIXED</name>
1052 <field name="FES" desc="Fifo empty status." bitrange="18:18"/> 1052 <value>0x1</value>
1053 <field name="WDCS" desc="Write Data/Command Select" bitrange="17:16"> 1053 </enum>
1054 <value name="CMD" value="0x0" desc="Write LCD register address"/> 1054 </field>
1055 <value name="DATA" value="0x1" desc="Write LCD register data"/> 1055 <field>
1056 <value name="RGB" value="0x2" desc="RGB565 Data FrameBuffer Transfer"/> 1056 <name>STRG</name>
1057 <value name="YUV" value="0x3" desc="YCbCr/YUV Data FrameBuffer Transfer"/> 1057 <desc>DRQ trig source.</desc>
1058 </field> 1058 <position>3</position>
1059 <field name="DEST" desc="RGB Decoder Destination." bitrange="15:15"/> 1059 <width>5</width>
1060 <field name="FORMATS" desc="RGB Format" bitrange="13:11"> 1060 <enum>
1061 <value name="RGB565_1" value="0x0" desc="16bit (RGB 565 1transfer)"/> 1061 <name>DAC</name>
1062 <value name="RGB666_1" value="0x1" desc="18bit (RGB 666 1transfer)"/> 1062 <value>0x6</value>
1063 <value name="RGB565_2" value="0x2" desc="8bit (RGB 565 2transfers)"/> 1063 </enum>
1064 <value name="RGB666_2" value="0x3" desc="9bit (RGB 666 2transfers)"/> 1064 <enum>
1065 <value name="RGB888_3" value="0x4" desc="8bit (RGB 888 3transfers)"/> 1065 <name>SDRAM</name>
1066 <value name="RGB666_3" value="0x5" desc="6bit (RGB 666 3transfers)"/> 1066 <value>0x10</value>
1067 </field> 1067 </enum>
1068 <field name="SEQ" desc="RGB Sequence" bitrange="10:10"> 1068 <enum>
1069 <value name="RGB" value="0x0" desc=""/> 1069 <name>IRAM</name>
1070 <value name="BGR" value="0x1" desc=""/> 1070 <value>0x11</value>
1071 </field> 1071 </enum>
1072 <field name="FWCS" desc="FIFO write channel select." bitrange="9:9"> 1072 <enum>
1073 <value name="SPECIAL" value="0x0" desc=""/> 1073 <name>SD</name>
1074 <value name="AHB" value="0x1" desc=""/> 1074 <value>0x16</value>
1075 </field> 1075 </enum>
1076 <field name="FRCS" desc="FIFO read channel select" bitrange="8:8"> 1076 <enum>
1077 <value name="SPECIAL" value="0x0" desc=""/> 1077 <name>OTG</name>
1078 <value name="AHB" value="0x1" desc=""/> 1078 <value>0x17</value>
1079 </field> 1079 </enum>
1080 <field name="EMDE" desc="FIFO Empty (Write) DRQ Enable." bitrange="7:7"/> 1080 <enum>
1081 <field name="EMIE" desc="FIFO Empty (Write) IRQ Enable." bitrange="6:6"/> 1081 <name>LCM</name>
1082 <field name="FUDE" desc="FIFO Full (Read) DRQ Enable." bitrange="5:5"/> 1082 <value>0x18</value>
1083 <field name="FUIE" desc="FIFO Full (Read) IRQ Enable." bitrange="4:4"/> 1083 </enum>
1084 <field name="EMCO" desc="FIFO Empty (Write) Condition." bitrange="3:3"> 1084 </field>
1085 <value name="EMPTY_4_8" value="0x0" desc=""/> 1085 <field>
1086 <value name="EMPTY_0_8" value="0x1" desc=""/> 1086 <name>STRANWID</name>
1087 </field> 1087 <position>1</position>
1088 <field name="EMIP" desc="FIFO Empty (Write) IRQ Pending Bit." bitrange="2:2"/> 1088 <width>2</width>
1089 <field name="FUIP" desc="FIFO Full (Read) IRQ Pending Bit." bitrange="1:1"/> 1089 <enum>
1090 <field name="ERP" desc="FIFO Error Pending Bit. Write 1 to the bit to clear it and reset the FIFO." bitrange="0:0"/> 1090 <name>WIDTH8</name>
1091 </reg> 1091 <value>0x0</value>
1092 <reg name="FIFODATA" desc=""> 1092 </enum>
1093 <addr name="FIFODATA" addr="0x4"/> 1093 <enum>
1094 </reg> 1094 <name>WIDTH16</name>
1095 <reg name="CLKCTL" desc=""> 1095 <value>0x1</value>
1096 <addr name="CLKCTL" addr="0x8"/> 1096 </enum>
1097 </reg> 1097 <enum>
1098 <reg name="FRAMECOUNT" desc=""> 1098 <name>WIDTH32</name>
1099 <addr name="FRAMECOUNT" addr="0xc"/> 1099 <value>0x2</value>
1100 </reg> 1100 </enum>
1101 </dev> 1101 </field>
1102 <field>
1103 <name>SFXS</name>
1104 <desc>Source Fix Size. If DFXS=0, DMA will transfer in 8bit mode when remain counter is less than STRANWID. If SFXS=1, DMA will always transfer in STRANWID.</desc>
1105 <position>0</position>
1106 </field>
1107 </register>
1108 </node>
1109 <node>
1110 <name>DMA_SRC</name>
1111 <instance>
1112 <name>DMA_SRC</name>
1113 <range>
1114 <first>0</first>
1115 <count>8</count>
1116 <base>0x104</base>
1117 <stride>0x20</stride>
1118 </range>
1119 </instance>
1120 <register/>
1121 </node>
1122 <node>
1123 <name>DMA_DST</name>
1124 <instance>
1125 <name>DMA_DST</name>
1126 <range>
1127 <first>0</first>
1128 <count>8</count>
1129 <base>0x108</base>
1130 <stride>0x20</stride>
1131 </range>
1132 </instance>
1133 <register/>
1134 </node>
1135 <node>
1136 <name>DMA_CNT</name>
1137 <instance>
1138 <name>DMA_CNT</name>
1139 <range>
1140 <first>0</first>
1141 <count>8</count>
1142 <base>0x10c</base>
1143 <stride>0x20</stride>
1144 </range>
1145 </instance>
1146 <register/>
1147 </node>
1148 <node>
1149 <name>DMA_REM</name>
1150 <instance>
1151 <name>DMA_REM</name>
1152 <range>
1153 <first>0</first>
1154 <count>8</count>
1155 <base>0x110</base>
1156 <stride>0x20</stride>
1157 </range>
1158 </instance>
1159 <register/>
1160 </node>
1161 <node>
1162 <name>DMA_CMD</name>
1163 <instance>
1164 <name>DMA_CMD</name>
1165 <range>
1166 <first>0</first>
1167 <count>8</count>
1168 <base>0x114</base>
1169 <stride>0x20</stride>
1170 </range>
1171 </instance>
1172 <register/>
1173 </node>
1174 </node>
1175 <node>
1176 <name>DSP</name>
1177 <title>Digital Signal Processor</title>
1178 <instance>
1179 <name>DSP</name>
1180 <address>0xb0050000</address>
1181 </instance>
1182 <node>
1183 <name>HDR</name>
1184 <instance>
1185 <name>HDR0</name>
1186 <address>0x0</address>
1187 </instance>
1188 <instance>
1189 <name>HDR1</name>
1190 <address>0x4</address>
1191 </instance>
1192 <instance>
1193 <name>HDR2</name>
1194 <address>0x8</address>
1195 </instance>
1196 <instance>
1197 <name>HDR3</name>
1198 <address>0xc</address>
1199 </instance>
1200 <instance>
1201 <name>HDR4</name>
1202 <address>0x10</address>
1203 </instance>
1204 <instance>
1205 <name>HDR5</name>
1206 <address>0x14</address>
1207 </instance>
1208 <instance>
1209 <name>HSR6</name>
1210 <address>0x18</address>
1211 </instance>
1212 <instance>
1213 <name>HSR7</name>
1214 <address>0x1c</address>
1215 </instance>
1216 <register>
1217 <desc>HIP data registers</desc>
1218 </register>
1219 </node>
1220 <node>
1221 <name>CTL</name>
1222 <instance>
1223 <name>CTL</name>
1224 <address>0x20</address>
1225 </instance>
1226 <register/>
1227 </node>
1228 </node>
1229 <node>
1230 <name>GPIO</name>
1231 <instance>
1232 <name>GPIO</name>
1233 <address>0xb01c0000</address>
1234 </instance>
1235 <node>
1236 <name>OUTEN</name>
1237 <instance>
1238 <name>AOUTEN</name>
1239 <address>0x0</address>
1240 </instance>
1241 <instance>
1242 <name>BOUTEN</name>
1243 <address>0xc</address>
1244 </instance>
1245 <register/>
1246 </node>
1247 <node>
1248 <name>INEN</name>
1249 <instance>
1250 <name>AINEN</name>
1251 <address>0x4</address>
1252 </instance>
1253 <instance>
1254 <name>BINEN</name>
1255 <address>0x10</address>
1256 </instance>
1257 <register/>
1258 </node>
1259 <node>
1260 <name>DAT</name>
1261 <instance>
1262 <name>ADAT</name>
1263 <address>0x8</address>
1264 </instance>
1265 <instance>
1266 <name>BDAT</name>
1267 <address>0x14</address>
1268 </instance>
1269 <register/>
1270 </node>
1271 <node>
1272 <name>MFCTL0</name>
1273 <instance>
1274 <name>MFCTL0</name>
1275 <address>0x18</address>
1276 </instance>
1277 <register>
1278 <field>
1279 <name>RESERVED31_25</name>
1280 <position>25</position>
1281 <width>7</width>
1282 </field>
1283 <field>
1284 <name>GPIOA2_0</name>
1285 <position>22</position>
1286 <width>3</width>
1287 <enum>
1288 <name>NAND_CLE_RB_ALE</name>
1289 <value>0x1</value>
1290 </enum>
1291 <enum>
1292 <name>LCD_RS_WD9_WD0</name>
1293 <value>0x2</value>
1294 </enum>
1295 <enum>
1296 <name>SD_CMD</name>
1297 <value>0x4</value>
1298 </enum>
1299 </field>
1300 <field>
1301 <name>CEB6</name>
1302 <position>20</position>
1303 <width>2</width>
1304 <enum>
1305 <name>LCD_CE</name>
1306 <value>0x2</value>
1307 </enum>
1308 <enum>
1309 <name>SD_CLK</name>
1310 <value>0x3</value>
1311 </enum>
1312 </field>
1313 <field>
1314 <name>RESERVED19_16</name>
1315 <position>16</position>
1316 <width>4</width>
1317 </field>
1318 <field>
1319 <name>CEB3</name>
1320 <position>14</position>
1321 <width>2</width>
1322 <enum>
1323 <name>NAND_CEB3</name>
1324 <value>0x1</value>
1325 </enum>
1326 <enum>
1327 <name>LCD_CE</name>
1328 <value>0x2</value>
1329 </enum>
1330 </field>
1331 <field>
1332 <name>CEB2</name>
1333 <position>12</position>
1334 <width>2</width>
1335 <enum>
1336 <name>NAND_CEB2</name>
1337 <value>0x1</value>
1338 </enum>
1339 <enum>
1340 <name>LCD_CE</name>
1341 <value>0x2</value>
1342 </enum>
1343 </field>
1344 <field>
1345 <name>CEB1</name>
1346 <position>10</position>
1347 <width>2</width>
1348 <enum>
1349 <name>NAND_CEB1</name>
1350 <value>0x1</value>
1351 </enum>
1352 <enum>
1353 <name>LCD_CE</name>
1354 <value>0x2</value>
1355 </enum>
1356 </field>
1357 <field>
1358 <name>CEB0</name>
1359 <position>8</position>
1360 <width>2</width>
1361 <enum>
1362 <name>NAND_CEB0</name>
1363 <value>0x1</value>
1364 </enum>
1365 <enum>
1366 <name>LCD_CE</name>
1367 <value>0x2</value>
1368 </enum>
1369 </field>
1370 <field>
1371 <name>WRRD</name>
1372 <position>6</position>
1373 <width>2</width>
1374 <enum>
1375 <name>NAND_WR_RD</name>
1376 <value>0x1</value>
1377 </enum>
1378 <enum>
1379 <name>LCD_WRB_RDB</name>
1380 <value>0x2</value>
1381 </enum>
1382 </field>
1383 <field>
1384 <name>NAND_D7_0</name>
1385 <position>3</position>
1386 <width>3</width>
1387 <enum>
1388 <name>NAND_D7_0</name>
1389 <value>0x1</value>
1390 </enum>
1391 <enum>
1392 <name>LCD_WD17_10</name>
1393 <value>0x2</value>
1394 </enum>
1395 </field>
1396 <field>
1397 <name>NAND_D15_8</name>
1398 <position>0</position>
1399 <width>3</width>
1400 <enum>
1401 <name>NAND_D15_8</name>
1402 <value>0x1</value>
1403 </enum>
1404 <enum>
1405 <name>LCD_WD8_1</name>
1406 <value>0x2</value>
1407 </enum>
1408 <enum>
1409 <name>SDR_D7_0</name>
1410 <value>0x4</value>
1411 </enum>
1412 </field>
1413 </register>
1414 </node>
1415 <node>
1416 <name>MFCTL1</name>
1417 <instance>
1418 <name>MFCTL1</name>
1419 <address>0x1c</address>
1420 </instance>
1421 <register>
1422 <field>
1423 <name>MFEN</name>
1424 <position>31</position>
1425 </field>
1426 <field>
1427 <name>RESERVED30_18</name>
1428 <position>18</position>
1429 <width>13</width>
1430 </field>
1431 <field>
1432 <name>SD2E</name>
1433 <position>17</position>
1434 </field>
1435 <field>
1436 <name>RBS</name>
1437 <position>16</position>
1438 </field>
1439 <field>
1440 <name>RESERVED15_12</name>
1441 <position>12</position>
1442 <width>4</width>
1443 </field>
1444 <field>
1445 <name>SIR0</name>
1446 <position>11</position>
1447 </field>
1448 <field>
1449 <name>SPTR</name>
1450 <position>9</position>
1451 <width>2</width>
1452 <enum>
1453 <name>I2C1_SCL_ADA</name>
1454 <value>0x1</value>
1455 </enum>
1456 <enum>
1457 <name>UART2_TX_RX</name>
1458 <value>0x2</value>
1459 </enum>
1460 </field>
1461 <field>
1462 <name>U2TR</name>
1463 <position>8</position>
1464 <enum>
1465 <name>UART2_TX_RX</name>
1466 <value>0x0</value>
1467 </enum>
1468 <enum>
1469 <name>I2C2_SCL_SDA</name>
1470 <value>0x1</value>
1471 </enum>
1472 </field>
1473 <field>
1474 <name>RESERVED7_6</name>
1475 <position>6</position>
1476 <width>2</width>
1477 </field>
1478 <field>
1479 <name>I2C1SS</name>
1480 <position>4</position>
1481 <width>2</width>
1482 <enum>
1483 <name>I2C1_SCL_SDA</name>
1484 <value>0x0</value>
1485 </enum>
1486 <enum>
1487 <name>UART2_TX_RX</name>
1488 <value>0x1</value>
1489 </enum>
1490 </field>
1491 <field>
1492 <name>RESERVED3_0</name>
1493 <position>0</position>
1494 <width>4</width>
1495 </field>
1496 </register>
1497 </node>
1498 </node>
1499 <node>
1500 <name>I2C</name>
1501 <instance>
1502 <name>I2C</name>
1503 <range>
1504 <first>1</first>
1505 <address>0xb0180000</address>
1506 <address>0xb0180020</address>
1507 </range>
1508 </instance>
1509 <node>
1510 <name>CTL</name>
1511 <instance>
1512 <name>CTL</name>
1513 <address>0x0</address>
1514 </instance>
1515 <register>
1516 <field>
1517 <name>RESERVED31_9</name>
1518 <position>9</position>
1519 <width>23</width>
1520 </field>
1521 <field>
1522 <name>PUEN</name>
1523 <desc>nternal Pull-up Resistor (4.7k) Enable</desc>
1524 <position>8</position>
1525 </field>
1526 <field>
1527 <name>EN</name>
1528 <desc>Block enable</desc>
1529 <position>7</position>
1530 </field>
1531 <field>
1532 <name>SIE</name>
1533 <desc>START Condition Generates IRQ Enable (only for slave mode)</desc>
1534 <position>6</position>
1535 </field>
1536 <field>
1537 <name>IRQE</name>
1538 <desc>IRQ Enable</desc>
1539 <position>5</position>
1540 </field>
1541 <field>
1542 <name>MS</name>
1543 <desc>Mode select</desc>
1544 <position>4</position>
1545 <enum>
1546 <name>MASTER</name>
1547 <value>0x0</value>
1548 </enum>
1549 <enum>
1550 <name>SLAVE</name>
1551 <value>0x1</value>
1552 </enum>
1553 </field>
1554 <field>
1555 <name>GBCC</name>
1556 <desc>Generating Bus Control Condition (only for master mode)</desc>
1557 <position>2</position>
1558 <width>2</width>
1559 <enum>
1560 <name>NOP</name>
1561 <value>0x0</value>
1562 </enum>
1563 <enum>
1564 <name>START</name>
1565 <value>0x1</value>
1566 </enum>
1567 <enum>
1568 <name>STOP</name>
1569 <value>0x2</value>
1570 </enum>
1571 <enum>
1572 <name>REPEATED_START</name>
1573 <value>0x3</value>
1574 </enum>
1575 </field>
1576 <field>
1577 <name>RB</name>
1578 <desc>Release Bus. Writing 1 to this bit will release the clock and data line to idle. MCU should write 1 to this bit after transmitting or receiving the last bit of
1579the whole transfer.
1580</desc>
1581 <position>1</position>
1582 </field>
1583 <field>
1584 <name>GRAS</name>
1585 <desc>Generating/Receiving Acknowledge Signal</desc>
1586 <position>0</position>
1587 </field>
1588 </register>
1589 </node>
1590 <node>
1591 <name>CLKDIV</name>
1592 <instance>
1593 <name>CLKDIV</name>
1594 <address>0x4</address>
1595 </instance>
1596 <register>
1597 <field>
1598 <name>RESERVED31_8</name>
1599 <position>8</position>
1600 <width>24</width>
1601 </field>
1602 <field>
1603 <name>CLKDIV</name>
1604 <desc>Clock Divider Factor (only for master mode). I2Cx clock (SCL) can select standard (100kbps) mode and fast (400kbps) mode. Calculating SCL is as follows: SCL=PCLK/(CLKDIV*16)
1605</desc>
1606 <position>0</position>
1607 <width>8</width>
1608 </field>
1609 </register>
1610 </node>
1611 <node>
1612 <name>STAT</name>
1613 <instance>
1614 <name>STAT</name>
1615 <address>0x8</address>
1616 </instance>
1617 <register>
1618 <field>
1619 <name>RESERVED31_8</name>
1620 <position>8</position>
1621 <width>24</width>
1622 </field>
1623 <field>
1624 <name>TRC</name>
1625 <desc>Transmit/Receive Complete Bit</desc>
1626 <position>7</position>
1627 </field>
1628 <field>
1629 <name>STPD</name>
1630 <desc>STOP Detect Bit </desc>
1631 <position>6</position>
1632 </field>
1633 <field>
1634 <name>STAD</name>
1635 <desc>START Detect Bit</desc>
1636 <position>5</position>
1637 </field>
1638 <field>
1639 <name>RWST</name>
1640 <desc>Read/Write Status Bit (only for Slave mode)</desc>
1641 <position>4</position>
1642 </field>
1643 <field>
1644 <name>LBST</name>
1645 <desc>Last Byte Status Bit</desc>
1646 <position>3</position>
1647 </field>
1648 <field>
1649 <name>IRQP</name>
1650 <desc>IRQ Pending Bit</desc>
1651 <position>2</position>
1652 </field>
1653 <field>
1654 <name>OVST</name>
1655 <desc>Overflow Status Bit</desc>
1656 <position>1</position>
1657 </field>
1658 <field>
1659 <name>WCO</name>
1660 <desc>Writing Collision Bit</desc>
1661 <position>0</position>
1662 </field>
1663 </register>
1664 </node>
1665 <node>
1666 <name>ADDR</name>
1667 <instance>
1668 <name>ADDR</name>
1669 <address>0xc</address>
1670 </instance>
1671 <register>
1672 <field>
1673 <name>RESERVED31_8</name>
1674 <position>8</position>
1675 <width>24</width>
1676 </field>
1677 <field>
1678 <name>SDAD</name>
1679 <desc>Slave Device Address</desc>
1680 <position>1</position>
1681 <width>7</width>
1682 </field>
1683 <field>
1684 <name>RWCM</name>
1685 <desc>Read/Write Control or Match</desc>
1686 <position>0</position>
1687 </field>
1688 </register>
1689 </node>
1690 <node>
1691 <name>DAT</name>
1692 <instance>
1693 <name>DAT</name>
1694 <address>0x10</address>
1695 </instance>
1696 <register>
1697 <field>
1698 <name>RESERVED31_8</name>
1699 <position>8</position>
1700 <width>24</width>
1701 </field>
1702 <field>
1703 <name>TXRXDAT</name>
1704 <desc>Transmit/Receive Data</desc>
1705 <position>0</position>
1706 <width>8</width>
1707 </field>
1708 </register>
1709 </node>
1710 </node>
1711 <node>
1712 <name>INTC</name>
1713 <title>Interrupt Controller</title>
1714 <instance>
1715 <name>INTC</name>
1716 <address>0xb0020000</address>
1717 </instance>
1718 <node>
1719 <name>PD</name>
1720 <instance>
1721 <name>PD</name>
1722 <address>0x0</address>
1723 </instance>
1724 <register/>
1725 </node>
1726 <node>
1727 <name>MSK</name>
1728 <instance>
1729 <name>MSK</name>
1730 <address>0x4</address>
1731 </instance>
1732 <register/>
1733 </node>
1734 <node>
1735 <name>CFG</name>
1736 <instance>
1737 <name>CFG0</name>
1738 <address>0x8</address>
1739 </instance>
1740 <instance>
1741 <name>CFG1</name>
1742 <address>0xc</address>
1743 </instance>
1744 <instance>
1745 <name>CFG2</name>
1746 <address>0x10</address>
1747 </instance>
1748 <register/>
1749 </node>
1750 <node>
1751 <name>EXTCTL</name>
1752 <instance>
1753 <name>EXTCTL</name>
1754 <address>0x14</address>
1755 </instance>
1756 <register/>
1757 </node>
1758 </node>
1759 <node>
1760 <name>IR</name>
1761 <instance>
1762 <name>IR</name>
1763 <address>0xb0160010</address>
1764 </instance>
1765 </node>
1766 <node>
1767 <name>KEY</name>
1768 <instance>
1769 <name>KEY</name>
1770 <address>0xb01a0000</address>
1771 </instance>
1772 </node>
1773 <node>
1774 <name>MCA</name>
1775 <title>Motion Compensation Accelerator</title>
1776 <instance>
1777 <name>MCA</name>
1778 <address>0xb0080000</address>
1779 </instance>
1780 <node>
1781 <name>CTL</name>
1782 <instance>
1783 <name>CTL</name>
1784 <address>0x0</address>
1785 </instance>
1786 <register/>
1787 </node>
1788 </node>
1789 <node>
1790 <name>MHA</name>
1791 <title>Media Hardware Accelerator</title>
1792 <instance>
1793 <name>MHA</name>
1794 <address>0xb00c0000</address>
1795 </instance>
1796 <node>
1797 <name>CTL</name>
1798 <instance>
1799 <name>CTL</name>
1800 <address>0x0</address>
1801 </instance>
1802 <register/>
1803 </node>
1804 <node>
1805 <name>CFG</name>
1806 <instance>
1807 <name>CFG</name>
1808 <address>0x4</address>
1809 </instance>
1810 <register/>
1811 </node>
1812 <node>
1813 <name>DCSCLx</name>
1814 <instance>
1815 <name>DCSCL0</name>
1816 <address>0x10</address>
1817 </instance>
1818 <instance>
1819 <name>DCSCL1</name>
1820 <address>0x14</address>
1821 </instance>
1822 <instance>
1823 <name>DCSCL2</name>
1824 <address>0x18</address>
1825 </instance>
1826 <instance>
1827 <name>DCSCL3</name>
1828 <address>0x1c</address>
1829 </instance>
1830 <register/>
1831 </node>
1832 <node>
1833 <name>QSCL</name>
1834 <instance>
1835 <name>QSCL</name>
1836 <address>0x20</address>
1837 </instance>
1838 <register/>
1839 </node>
1840 </node>
1841 <node>
1842 <name>NAND</name>
1843 <title>NAND Flash Interface</title>
1844 <instance>
1845 <name>NAND</name>
1846 <address>0xb00a0000</address>
1847 </instance>
1848 <node>
1849 <name>CTL</name>
1850 <instance>
1851 <name>CTL</name>
1852 <address>0x0</address>
1853 </instance>
1854 <register/>
1855 </node>
1856 <node>
1857 <name>STATUS</name>
1858 <instance>
1859 <name>STATUS</name>
1860 <address>0x4</address>
1861 </instance>
1862 <register/>
1863 </node>
1864 <node>
1865 <name>FIFOTIM</name>
1866 <instance>
1867 <name>FIFOTIM</name>
1868 <address>0x8</address>
1869 </instance>
1870 <register/>
1871 </node>
1872 <node>
1873 <name>CLKCTL</name>
1874 <instance>
1875 <name>CLKCTL</name>
1876 <address>0xc</address>
1877 </instance>
1878 <register/>
1879 </node>
1880 <node>
1881 <name>BYTECNT</name>
1882 <instance>
1883 <name>BYTECNT</name>
1884 <address>0x10</address>
1885 </instance>
1886 <register/>
1887 </node>
1888 <node>
1889 <name>ADDR01</name>
1890 <instance>
1891 <name>ADDR01</name>
1892 <address>0x14</address>
1893 </instance>
1894 <register/>
1895 </node>
1896 <node>
1897 <name>ADDR23</name>
1898 <instance>
1899 <name>ADDR23</name>
1900 <address>0x18</address>
1901 </instance>
1902 <register/>
1903 </node>
1904 <node>
1905 <name>ADDR45</name>
1906 <instance>
1907 <name>ADDR45</name>
1908 <address>0x1c</address>
1909 </instance>
1910 <register/>
1911 </node>
1912 <node>
1913 <name>ADDR67</name>
1914 <instance>
1915 <name>ADDR67</name>
1916 <address>0x20</address>
1917 </instance>
1918 <register/>
1919 </node>
1920 <node>
1921 <name>BUF</name>
1922 <instance>
1923 <name>BUF0</name>
1924 <address>0x24</address>
1925 </instance>
1926 <instance>
1927 <name>BUF1</name>
1928 <address>0x28</address>
1929 </instance>
1930 <register/>
1931 </node>
1932 <node>
1933 <name>CMD</name>
1934 <instance>
1935 <name>CMD</name>
1936 <address>0x2c</address>
1937 </instance>
1938 <register/>
1939 </node>
1940 <node>
1941 <name>ECCCTL</name>
1942 <instance>
1943 <name>ECCCTL</name>
1944 <address>0x30</address>
1945 </instance>
1946 <register/>
1947 </node>
1948 <node>
1949 <name>HAMECC</name>
1950 <instance>
1951 <name>HAMECC0</name>
1952 <address>0x34</address>
1953 </instance>
1954 <instance>
1955 <name>HAMECC1</name>
1956 <address>0x38</address>
1957 </instance>
1958 <instance>
1959 <name>HAMECC2</name>
1960 <address>0x3c</address>
1961 </instance>
1962 <register/>
1963 </node>
1964 <node>
1965 <name>HAMCEC</name>
1966 <instance>
1967 <name>HAMCEC</name>
1968 <address>0x40</address>
1969 </instance>
1970 <register/>
1971 </node>
1972 <node>
1973 <name>RSE</name>
1974 <instance>
1975 <name>RSE0</name>
1976 <address>0x44</address>
1977 </instance>
1978 <instance>
1979 <name>RSE1</name>
1980 <address>0x48</address>
1981 </instance>
1982 <instance>
1983 <name>RSE2</name>
1984 <address>0x4c</address>
1985 </instance>
1986 <instance>
1987 <name>RSE3</name>
1988 <address>0x50</address>
1989 </instance>
1990 <register/>
1991 </node>
1992 <node>
1993 <name>RSPS</name>
1994 <instance>
1995 <name>RSPS0</name>
1996 <address>0x54</address>
1997 </instance>
1998 <instance>
1999 <name>RSPS1</name>
2000 <address>0x58</address>
2001 </instance>
2002 <instance>
2003 <name>RSPS2</name>
2004 <address>0x5c</address>
2005 </instance>
2006 <register/>
2007 </node>
2008 <node>
2009 <name>FIFODATA</name>
2010 <instance>
2011 <name>FIFODATA</name>
2012 <address>0x60</address>
2013 </instance>
2014 <register/>
2015 </node>
2016 <node>
2017 <name>DEBUG</name>
2018 <instance>
2019 <name>DEBUG</name>
2020 <address>0x70</address>
2021 </instance>
2022 <register/>
2023 </node>
2024 </node>
2025 <node>
2026 <name>PCM</name>
2027 <instance>
2028 <name>PCM</name>
2029 <address>0xb0150000</address>
2030 </instance>
2031 </node>
2032 <node>
2033 <name>PCNT</name>
2034 <title>Performance Counters</title>
2035 <desc>The base address is not clear!</desc>
2036 <instance>
2037 <name>PCNT</name>
2038 <address>0xb003c000</address>
2039 </instance>
2040 <node>
2041 <name>CTL</name>
2042 <instance>
2043 <name>CTL</name>
2044 <address>0x0</address>
2045 </instance>
2046 <register/>
2047 </node>
2048 <node>
2049 <name>PCx</name>
2050 <instance>
2051 <name>PC0</name>
2052 <address>0x4</address>
2053 </instance>
2054 <instance>
2055 <name>PC1</name>
2056 <address>0x8</address>
2057 </instance>
2058 <register/>
2059 </node>
2060 </node>
2061 <node>
2062 <name>PMU</name>
2063 <title>Power Management Unit</title>
2064 <instance>
2065 <name>PMU</name>
2066 <address>0xb0000000</address>
2067 </instance>
2068 <node>
2069 <name>CTL</name>
2070 <instance>
2071 <name>CTL</name>
2072 <address>0x0</address>
2073 </instance>
2074 <register>
2075 <field>
2076 <name>LBRM</name>
2077 <position>31</position>
2078 </field>
2079 <field>
2080 <name>VCVS</name>
2081 <position>28</position>
2082 <width>3</width>
2083 </field>
2084 <field>
2085 <name>LBNM</name>
2086 <position>27</position>
2087 </field>
2088 <field>
2089 <name>VDVS</name>
2090 <position>24</position>
2091 <width>3</width>
2092 </field>
2093 <field>
2094 <name>VCDE</name>
2095 <position>23</position>
2096 </field>
2097 <field>
2098 <name>VCVD</name>
2099 <position>20</position>
2100 <width>3</width>
2101 </field>
2102 <field>
2103 <name>VDDE</name>
2104 <position>19</position>
2105 </field>
2106 <field>
2107 <name>VDVD</name>
2108 <position>16</position>
2109 <width>3</width>
2110 </field>
2111 <field>
2112 <name>BLEN</name>
2113 <position>15</position>
2114 </field>
2115 <field>
2116 <name>VCOE</name>
2117 <position>14</position>
2118 </field>
2119 <field>
2120 <name>LA6E</name>
2121 <position>13</position>
2122 </field>
2123 <field>
2124 <name>LA4E</name>
2125 <position>12</position>
2126 </field>
2127 <field>
2128 <name>IBIAS</name>
2129 <position>10</position>
2130 <width>2</width>
2131 </field>
2132 <field>
2133 <name>OSCFREQ</name>
2134 <position>8</position>
2135 <width>2</width>
2136 </field>
2137 <field>
2138 <name>DC1M</name>
2139 <position>7</position>
2140 </field>
2141 <field>
2142 <name>DC2M</name>
2143 <position>6</position>
2144 </field>
2145 <field>
2146 <name>BLVS</name>
2147 <position>3</position>
2148 <width>3</width>
2149 </field>
2150 <field>
2151 <name>VDV0</name>
2152 <position>2</position>
2153 </field>
2154 <field>
2155 <name>PWRM</name>
2156 <position>0</position>
2157 <width>2</width>
2158 </field>
2159 </register>
2160 </node>
2161 <node>
2162 <name>LRADC</name>
2163 <instance>
2164 <name>LRADC</name>
2165 <address>0x4</address>
2166 </instance>
2167 <register>
2168 <field>
2169 <name>RESERVED31_28</name>
2170 <position>28</position>
2171 <width>4</width>
2172 </field>
2173 <field>
2174 <name>REMOADC4</name>
2175 <position>24</position>
2176 <width>4</width>
2177 </field>
2178 <field>
2179 <name>RESERVED23_20</name>
2180 <position>22</position>
2181 <width>2</width>
2182 </field>
2183 <field>
2184 <name>BATADC6</name>
2185 <position>16</position>
2186 <width>6</width>
2187 </field>
2188 <field>
2189 <name>RESERVED15_14</name>
2190 <position>14</position>
2191 <width>2</width>
2192 </field>
2193 <field>
2194 <name>TEMPADC6</name>
2195 <position>8</position>
2196 <width>6</width>
2197 </field>
2198 <field>
2199 <name>RESERVED7_0</name>
2200 <position>0</position>
2201 <width>8</width>
2202 </field>
2203 </register>
2204 </node>
2205 <node>
2206 <name>CHG</name>
2207 <instance>
2208 <name>CHG</name>
2209 <address>0x8</address>
2210 </instance>
2211 <register>
2212 <field>
2213 <name>EN</name>
2214 <position>31</position>
2215 </field>
2216 <field>
2217 <name>CURRENT</name>
2218 <position>28</position>
2219 <width>3</width>
2220 <enum>
2221 <name>CURRENT_50mA</name>
2222 <value>0x0</value>
2223 </enum>
2224 <enum>
2225 <name>CURRENT_100mA</name>
2226 <value>0x1</value>
2227 </enum>
2228 <enum>
2229 <name>CURRENT_150mA</name>
2230 <value>0x2</value>
2231 </enum>
2232 <enum>
2233 <name>CURRENT_200mA</name>
2234 <value>0x3</value>
2235 </enum>
2236 <enum>
2237 <name>CURRENT_250mA</name>
2238 <value>0x4</value>
2239 </enum>
2240 <enum>
2241 <name>CURRENT_300mA</name>
2242 <value>0x5</value>
2243 </enum>
2244 <enum>
2245 <name>CURRENT_400mA</name>
2246 <value>0x6</value>
2247 </enum>
2248 <enum>
2249 <name>CURRENT_500mA</name>
2250 <value>0x7</value>
2251 </enum>
2252 </field>
2253 <field>
2254 <name>STAT</name>
2255 <position>27</position>
2256 <enum>
2257 <name>DISCHARGING</name>
2258 <value>0x0</value>
2259 </enum>
2260 <enum>
2261 <name>CHARGING</name>
2262 <value>0x1</value>
2263 </enum>
2264 </field>
2265 <field>
2266 <name>CHGPHASE</name>
2267 <position>25</position>
2268 <width>2</width>
2269 <enum>
2270 <name>RESERVED</name>
2271 <value>0x0</value>
2272 </enum>
2273 <enum>
2274 <name>PRECHARGE</name>
2275 <value>0x1</value>
2276 </enum>
2277 <enum>
2278 <name>CC</name>
2279 <value>0x2</value>
2280 </enum>
2281 <enum>
2282 <name>CV</name>
2283 <value>0x3</value>
2284 </enum>
2285 </field>
2286 <field>
2287 <name>RESERVED24_16</name>
2288 <position>16</position>
2289 <width>9</width>
2290 </field>
2291 <field>
2292 <name>PBLS</name>
2293 <position>15</position>
2294 </field>
2295 <field>
2296 <name>PPHS</name>
2297 <position>14</position>
2298 </field>
2299 <field>
2300 <name>RESERVED13</name>
2301 <position>13</position>
2302 </field>
2303 <field>
2304 <name>PDUT</name>
2305 <position>8</position>
2306 <width>5</width>
2307 </field>
2308 <field>
2309 <name>RESERVED7</name>
2310 <position>7</position>
2311 </field>
2312 <field>
2313 <name>BLV0</name>
2314 <position>6</position>
2315 </field>
2316 <field>
2317 <name>TMPSET</name>
2318 <position>4</position>
2319 <width>2</width>
2320 <enum>
2321 <name>TEMP_40C</name>
2322 <value>0x0</value>
2323 </enum>
2324 <enum>
2325 <name>TEMP_45C</name>
2326 <value>0x1</value>
2327 </enum>
2328 <enum>
2329 <name>TEMP_50C</name>
2330 <value>0x2</value>
2331 </enum>
2332 <enum>
2333 <name>TEMP_55C</name>
2334 <value>0x3</value>
2335 </enum>
2336 </field>
2337 <field>
2338 <name>LBNMIVS</name>
2339 <position>2</position>
2340 <width>2</width>
2341 <enum>
2342 <name>VOLTAGE_2_9</name>
2343 <value>0x0</value>
2344 </enum>
2345 <enum>
2346 <name>VOLTAGE_3_1</name>
2347 <value>0x1</value>
2348 </enum>
2349 <enum>
2350 <name>VOLTAGE_3_3</name>
2351 <value>0x2</value>
2352 </enum>
2353 <enum>
2354 <name>VOLTAGE_3_5</name>
2355 <value>0x3</value>
2356 </enum>
2357 </field>
2358 <field>
2359 <name>LBRVS</name>
2360 <position>0</position>
2361 <width>2</width>
2362 <enum>
2363 <name>VOLTAGE_2_7</name>
2364 <value>0x0</value>
2365 </enum>
2366 <enum>
2367 <name>VOLTAGE_2_9</name>
2368 <value>0x1</value>
2369 </enum>
2370 <enum>
2371 <name>VOLTAGE_3_1</name>
2372 <value>0x2</value>
2373 </enum>
2374 <enum>
2375 <name>VOLTAGE_3_3</name>
2376 <value>0x3</value>
2377 </enum>
2378 </field>
2379 </register>
2380 </node>
2381 </node>
2382 <node>
2383 <name>RTCWDT</name>
2384 <title>Real Time Clock, Timers and Watchdog</title>
2385 <instance>
2386 <name>RTC</name>
2387 <address>0xb0018000</address>
2388 </instance>
2389 <node>
2390 <name>CTL</name>
2391 <instance>
2392 <name>CTL</name>
2393 <address>0x0</address>
2394 </instance>
2395 <register/>
2396 </node>
2397 <node>
2398 <name>DHMS</name>
2399 <instance>
2400 <name>DHMS</name>
2401 <address>0x4</address>
2402 </instance>
2403 <register>
2404 <field>
2405 <name>RESERVED31_27</name>
2406 <position>27</position>
2407 <width>5</width>
2408 </field>
2409 <field>
2410 <name>DAY</name>
2411 <position>24</position>
2412 <width>3</width>
2413 </field>
2414 <field>
2415 <name>RESERVED23_21</name>
2416 <position>21</position>
2417 <width>3</width>
2418 </field>
2419 <field>
2420 <name>HOUR</name>
2421 <position>16</position>
2422 <width>5</width>
2423 </field>
2424 <field>
2425 <name>RESERVED15_14</name>
2426 <position>14</position>
2427 <width>2</width>
2428 </field>
2429 <field>
2430 <name>MIN</name>
2431 <position>8</position>
2432 <width>6</width>
2433 </field>
2434 <field>
2435 <name>RESERVED7_6</name>
2436 <position>6</position>
2437 <width>2</width>
2438 </field>
2439 <field>
2440 <name>SEC</name>
2441 <position>0</position>
2442 <width>6</width>
2443 </field>
2444 </register>
2445 </node>
2446 <node>
2447 <name>YMD</name>
2448 <instance>
2449 <name>YMD</name>
2450 <address>0x8</address>
2451 </instance>
2452 <register>
2453 <field>
2454 <name>RESERVED31</name>
2455 <position>31</position>
2456 </field>
2457 <field>
2458 <name>CENT</name>
2459 <position>24</position>
2460 <width>7</width>
2461 </field>
2462 <field>
2463 <name>RESERVED23</name>
2464 <position>23</position>
2465 </field>
2466 <field>
2467 <name>YEAR</name>
2468 <position>16</position>
2469 <width>7</width>
2470 </field>
2471 <field>
2472 <name>RESERVED15_12</name>
2473 <position>12</position>
2474 <width>4</width>
2475 </field>
2476 <field>
2477 <name>MON</name>
2478 <position>8</position>
2479 <width>4</width>
2480 </field>
2481 <field>
2482 <name>RESERVED7_5</name>
2483 <position>5</position>
2484 <width>3</width>
2485 </field>
2486 <field>
2487 <name>DATE</name>
2488 <position>0</position>
2489 <width>5</width>
2490 </field>
2491 </register>
2492 </node>
2493 <node>
2494 <name>DHMSALM</name>
2495 <instance>
2496 <name>DHMSALM</name>
2497 <address>0xc</address>
2498 </instance>
2499 <register>
2500 <field>
2501 <name>RESERVED31_21</name>
2502 <position>21</position>
2503 <width>11</width>
2504 </field>
2505 <field>
2506 <name>HOURAL</name>
2507 <position>16</position>
2508 <width>5</width>
2509 </field>
2510 <field>
2511 <name>RESERVED15_14</name>
2512 <position>14</position>
2513 <width>2</width>
2514 </field>
2515 <field>
2516 <name>MINAL</name>
2517 <position>8</position>
2518 <width>6</width>
2519 </field>
2520 <field>
2521 <name>RESERVED7_6</name>
2522 <position>6</position>
2523 <width>2</width>
2524 </field>
2525 <field>
2526 <name>SECAL</name>
2527 <position>0</position>
2528 <width>6</width>
2529 </field>
2530 </register>
2531 </node>
2532 <node>
2533 <name>YMDALM</name>
2534 <instance>
2535 <name>YMDALM</name>
2536 <address>0x10</address>
2537 </instance>
2538 <register>
2539 <field>
2540 <name>RESERVED31_23</name>
2541 <position>23</position>
2542 <width>9</width>
2543 </field>
2544 <field>
2545 <name>YEARAL</name>
2546 <position>16</position>
2547 <width>7</width>
2548 </field>
2549 <field>
2550 <name>RESERVED15_12</name>
2551 <position>12</position>
2552 <width>4</width>
2553 </field>
2554 <field>
2555 <name>MONAL</name>
2556 <position>8</position>
2557 <width>4</width>
2558 </field>
2559 <field>
2560 <name>RESERVED7_5</name>
2561 <position>5</position>
2562 <width>3</width>
2563 </field>
2564 <field>
2565 <name>DATEAL</name>
2566 <position>0</position>
2567 <width>5</width>
2568 </field>
2569 </register>
2570 </node>
2571 <node>
2572 <name>WDCTL</name>
2573 <instance>
2574 <name>WDCTL</name>
2575 <address>0x14</address>
2576 </instance>
2577 <register/>
2578 </node>
2579 <node>
2580 <name>TxCTL</name>
2581 <instance>
2582 <name>T0CTL</name>
2583 <address>0x18</address>
2584 </instance>
2585 <instance>
2586 <name>T1CTL</name>
2587 <address>0x20</address>
2588 </instance>
2589 <register/>
2590 </node>
2591 <node>
2592 <name>Tx</name>
2593 <instance>
2594 <name>T0</name>
2595 <address>0x1c</address>
2596 </instance>
2597 <instance>
2598 <name>T1</name>
2599 <address>0x24</address>
2600 </instance>
2601 <register/>
2602 </node>
2603 </node>
2604 <node>
2605 <name>SD</name>
2606 <title>SD/MMC Interface</title>
2607 <instance>
2608 <name>SD</name>
2609 <address>0xb00b0000</address>
2610 </instance>
2611 <node>
2612 <name>CTL</name>
2613 <instance>
2614 <name>CTL</name>
2615 <address>0x0</address>
2616 </instance>
2617 <register/>
2618 </node>
2619 <node>
2620 <name>CMDRSP</name>
2621 <instance>
2622 <name>CMDRSP</name>
2623 <address>0x4</address>
2624 </instance>
2625 <register/>
2626 </node>
2627 <node>
2628 <name>RW</name>
2629 <instance>
2630 <name>RW</name>
2631 <address>0x8</address>
2632 </instance>
2633 <register/>
2634 </node>
2635 <node>
2636 <name>FIFOCTL</name>
2637 <instance>
2638 <name>FIFOCTL</name>
2639 <address>0xc</address>
2640 </instance>
2641 <register/>
2642 </node>
2643 <node>
2644 <name>CMD</name>
2645 <instance>
2646 <name>CMD</name>
2647 <address>0x10</address>
2648 </instance>
2649 <register/>
2650 </node>
2651 <node>
2652 <name>ARG</name>
2653 <instance>
2654 <name>ARG</name>
2655 <address>0x14</address>
2656 </instance>
2657 <register/>
2658 </node>
2659 <node>
2660 <name>CRC7</name>
2661 <instance>
2662 <name>CRC7</name>
2663 <address>0x18</address>
2664 </instance>
2665 <register/>
2666 </node>
2667 <node>
2668 <name>RSPBUFx</name>
2669 <instance>
2670 <name>RSPBUF0</name>
2671 <address>0x1c</address>
2672 </instance>
2673 <instance>
2674 <name>RSPBUF1</name>
2675 <address>0x20</address>
2676 </instance>
2677 <instance>
2678 <name>RSPBUF2</name>
2679 <address>0x24</address>
2680 </instance>
2681 <instance>
2682 <name>RSPBUF3</name>
2683 <address>0x28</address>
2684 </instance>
2685 <instance>
2686 <name>RSPBUF4</name>
2687 <address>0x2c</address>
2688 </instance>
2689 <register/>
2690 </node>
2691 <node>
2692 <name>DAT</name>
2693 <instance>
2694 <name>DAT</name>
2695 <address>0x30</address>
2696 </instance>
2697 <register/>
2698 </node>
2699 <node>
2700 <name>CLK</name>
2701 <instance>
2702 <name>CLK</name>
2703 <address>0x34</address>
2704 </instance>
2705 <register/>
2706 </node>
2707 <node>
2708 <name>BYTECNT</name>
2709 <instance>
2710 <name>BYTECNT</name>
2711 <address>0x38</address>
2712 </instance>
2713 <register/>
2714 </node>
2715 </node>
2716 <node>
2717 <name>SDR</name>
2718 <title>SDRAM Interface</title>
2719 <instance>
2720 <name>SDR</name>
2721 <address>0xb0070000</address>
2722 </instance>
2723 <node>
2724 <name>CTL</name>
2725 <instance>
2726 <name>CTL</name>
2727 <address>0x0</address>
2728 </instance>
2729 <register/>
2730 </node>
2731 <node>
2732 <name>ADDRCFG</name>
2733 <instance>
2734 <name>ADDRCFG</name>
2735 <address>0x4</address>
2736 </instance>
2737 <register/>
2738 </node>
2739 <node>
2740 <name>EN</name>
2741 <instance>
2742 <name>EN</name>
2743 <address>0x8</address>
2744 </instance>
2745 <register>
2746 <field>
2747 <name>RESERVED31_1</name>
2748 <position>1</position>
2749 <width>31</width>
2750 </field>
2751 <field>
2752 <name>EN</name>
2753 <position>0</position>
2754 </field>
2755 </register>
2756 </node>
2757 <node>
2758 <name>CMD</name>
2759 <instance>
2760 <name>CMD</name>
2761 <address>0xc</address>
2762 </instance>
2763 <register/>
2764 </node>
2765 <node>
2766 <name>STAT</name>
2767 <instance>
2768 <name>STAT</name>
2769 <address>0x10</address>
2770 </instance>
2771 <register/>
2772 </node>
2773 <node>
2774 <name>RFSH</name>
2775 <instance>
2776 <name>RFSH</name>
2777 <address>0x14</address>
2778 </instance>
2779 <register/>
2780 </node>
2781 <node>
2782 <name>MODE</name>
2783 <instance>
2784 <name>MODE</name>
2785 <address>0x18</address>
2786 </instance>
2787 <register/>
2788 </node>
2789 <node>
2790 <name>MOBILE</name>
2791 <instance>
2792 <name>MOBILE</name>
2793 <address>0x1c</address>
2794 </instance>
2795 <register/>
2796 </node>
2797 </node>
2798 <node>
2799 <name>SPDIF</name>
2800 <title>Sony Philips Digital Interface</title>
2801 <instance>
2802 <name>SPDIF</name>
2803 <address>0xb0140000</address>
2804 </instance>
2805 </node>
2806 <node>
2807 <name>SPI</name>
2808 <instance>
2809 <name>SPI</name>
2810 <address>0xb0190000</address>
2811 </instance>
2812 </node>
2813 <node>
2814 <name>SRAMOC</name>
2815 <title>SRAM on Chip</title>
2816 <instance>
2817 <name>SRAMOC</name>
2818 <address>0xb0030000</address>
2819 </instance>
2820 <node>
2821 <name>CTL</name>
2822 <instance>
2823 <name>CTL</name>
2824 <address>0x0</address>
2825 </instance>
2826 <register/>
2827 </node>
2828 <node>
2829 <name>STAT</name>
2830 <instance>
2831 <name>STAT</name>
2832 <address>0x4</address>
2833 </instance>
2834 <register/>
2835 </node>
2836 </node>
2837 <node>
2838 <name>TP</name>
2839 <instance>
2840 <name>TP</name>
2841 <address>0xb0120000</address>
2842 </instance>
2843 </node>
2844 <node>
2845 <name>UART</name>
2846 <instance>
2847 <name>UART</name>
2848 <range>
2849 <first>1</first>
2850 <address>0xb0160000</address>
2851 <address>0xb0160020</address>
2852 </range>
2853 </instance>
2854 </node>
2855 <node>
2856 <name>UDC</name>
2857 <title>Usb Device Controller</title>
2858 <desc>CAST cusb2-otg IP core</desc>
2859 <instance>
2860 <name>UDC</name>
2861 <address>0xb00e0000</address>
2862 </instance>
2863 <node>
2864 <name>EP0BC</name>
2865 <instance>
2866 <name>OUT0BC</name>
2867 <address>0x0</address>
2868 </instance>
2869 <instance>
2870 <name>IN0BC</name>
2871 <address>0x1</address>
2872 </instance>
2873 <register>
2874 <desc>ep0 byte count register</desc>
2875 <field>
2876 <name>RESERVED</name>
2877 <position>8</position>
2878 <width>24</width>
2879 </field>
2880 <field>
2881 <name>BC</name>
2882 <position>0</position>
2883 <width>8</width>
2884 </field>
2885 </register>
2886 </node>
2887 <node>
2888 <name>EP0CS</name>
2889 <instance>
2890 <name>EP0CS</name>
2891 <address>0x2</address>
2892 </instance>
2893 <register>
2894 <field>
2895 <name>RESERVED</name>
2896 <position>8</position>
2897 <width>24</width>
2898 </field>
2899 <field>
2900 <name>OUT_BUSY</name>
2901 <position>3</position>
2902 </field>
2903 <field>
2904 <name>IN_BUSY</name>
2905 <position>2</position>
2906 </field>
2907 <field>
2908 <name>NAK</name>
2909 <desc>Writing 1 clears</desc>
2910 <position>1</position>
2911 </field>
2912 <field>
2913 <name>STALL</name>
2914 <position>0</position>
2915 </field>
2916 </register>
2917 </node>
2918 <node>
2919 <name>BCL</name>
2920 <instance>
2921 <name>OUT1BCL</name>
2922 <address>0x8</address>
2923 </instance>
2924 <instance>
2925 <name>IN1BCL</name>
2926 <address>0xc</address>
2927 </instance>
2928 <instance>
2929 <name>OUT2BCL</name>
2930 <address>0x10</address>
2931 </instance>
2932 <instance>
2933 <name>IN2BCL</name>
2934 <address>0x14</address>
2935 </instance>
2936 <register>
2937 <desc>Endpoint byte count LSB register</desc>
2938 </register>
2939 </node>
2940 <node>
2941 <name>BCH</name>
2942 <instance>
2943 <name>OUT1BCH</name>
2944 <address>0x9</address>
2945 </instance>
2946 <instance>
2947 <name>IN1BCH</name>
2948 <address>0xd</address>
2949 </instance>
2950 <instance>
2951 <name>OUT2BCH</name>
2952 <address>0x11</address>
2953 </instance>
2954 <instance>
2955 <name>IN2BCH</name>
2956 <address>0x15</address>
2957 </instance>
2958 <register>
2959 <desc>Endpoint byte count MSB</desc>
2960 </register>
2961 </node>
2962 <node>
2963 <name>CON</name>
2964 <instance>
2965 <name>OUT1CON</name>
2966 <address>0xa</address>
2967 </instance>
2968 <instance>
2969 <name>IN1CON</name>
2970 <address>0xe</address>
2971 </instance>
2972 <instance>
2973 <name>OUT2CON</name>
2974 <address>0x12</address>
2975 </instance>
2976 <instance>
2977 <name>IN2CON</name>
2978 <address>0x16</address>
2979 </instance>
2980 <register>
2981 <desc>Endpoint configuration register</desc>
2982 <field>
2983 <name>EP_ENABLE</name>
2984 <position>7</position>
2985 </field>
2986 <field>
2987 <name>STALL</name>
2988 <position>6</position>
2989 </field>
2990 <field>
2991 <name>EP_TYPE</name>
2992 <position>2</position>
2993 <width>2</width>
2994 <enum>
2995 <name>RESERVED</name>
2996 <value>0x0</value>
2997 </enum>
2998 <enum>
2999 <name>ISOCHRONOUS</name>
3000 <value>0x1</value>
3001 </enum>
3002 <enum>
3003 <name>BULK</name>
3004 <value>0x2</value>
3005 </enum>
3006 <enum>
3007 <name>INTERRUPT</name>
3008 <value>0x3</value>
3009 </enum>
3010 </field>
3011 <field>
3012 <name>SUBFIFOS</name>
3013 <position>0</position>
3014 <width>2</width>
3015 <enum>
3016 <name>SINGLE</name>
3017 <value>0x0</value>
3018 </enum>
3019 <enum>
3020 <name>DOUBLE</name>
3021 <value>0x1</value>
3022 </enum>
3023 <enum>
3024 <name>TRIPLE</name>
3025 <value>0x2</value>
3026 </enum>
3027 <enum>
3028 <name>QUAD</name>
3029 <value>0x3</value>
3030 </enum>
3031 </field>
3032 </register>
3033 </node>
3034 <node>
3035 <name>CS</name>
3036 <instance>
3037 <name>OUT1CS</name>
3038 <address>0xb</address>
3039 </instance>
3040 <instance>
3041 <name>IN1CS</name>
3042 <address>0xf</address>
3043 </instance>
3044 <instance>
3045 <name>OUT2CS</name>
3046 <address>0x13</address>
3047 </instance>
3048 <instance>
3049 <name>IN2CS</name>
3050 <address>0x17</address>
3051 </instance>
3052 <register>
3053 <desc>Endpoint status register</desc>
3054 <field>
3055 <name>AUTO</name>
3056 <position>4</position>
3057 </field>
3058 <field>
3059 <name>NPACK1</name>
3060 <position>3</position>
3061 </field>
3062 <field>
3063 <name>NPACK0</name>
3064 <position>2</position>
3065 </field>
3066 <field>
3067 <name>BUSY</name>
3068 <position>1</position>
3069 </field>
3070 <field>
3071 <name>ERROR</name>
3072 <position>0</position>
3073 </field>
3074 </register>
3075 </node>
3076 <node>
3077 <name>FIFODAT</name>
3078 <instance>
3079 <name>FIFO1DAT</name>
3080 <address>0x84</address>
3081 </instance>
3082 <instance>
3083 <name>FIFO2DAT</name>
3084 <address>0x88</address>
3085 </instance>
3086 <register>
3087 <desc>Endpoint FIFO</desc>
3088 </register>
3089 </node>
3090 <node>
3091 <name>EP0DAT</name>
3092 <instance>
3093 <name>EP0INDAT</name>
3094 <address>0x100</address>
3095 </instance>
3096 <instance>
3097 <name>EP0OUTDAT</name>
3098 <address>0x140</address>
3099 </instance>
3100 <register>
3101 <desc>Endpoint 0 buffers each 64 bytes long.</desc>
3102 </register>
3103 </node>
3104 <node>
3105 <name>SETUPDAT</name>
3106 <instance>
3107 <name>SETUPDAT</name>
3108 <address>0x180</address>
3109 </instance>
3110 <register>
3111 <desc>SETUP packet buffer</desc>
3112 </register>
3113 </node>
3114 <node>
3115 <name>EPIRQ</name>
3116 <instance>
3117 <name>IN04IRQ</name>
3118 <address>0x188</address>
3119 </instance>
3120 <instance>
3121 <name>OUT04IRQ</name>
3122 <address>0x18a</address>
3123 </instance>
3124 <register>
3125 <desc>Endpoint irq flag register</desc>
3126 <field>
3127 <name>EP_NUM</name>
3128 <position>0</position>
3129 <width>3</width>
3130 </field>
3131 </register>
3132 </node>
3133 <node>
3134 <name>USBIRQ</name>
3135 <instance>
3136 <name>USBIRQ</name>
3137 <address>0x18c</address>
3138 </instance>
3139 <register>
3140 <desc>General usb core irq flags</desc>
3141 <field>
3142 <name>HS</name>
3143 <desc>Enter high speed operation. Set by core on connection.</desc>
3144 <position>5</position>
3145 </field>
3146 <field>
3147 <name>RESET</name>
3148 <desc>Asserted on usb reset.</desc>
3149 <position>4</position>
3150 </field>
3151 <field>
3152 <name>SUSPEND</name>
3153 <position>3</position>
3154 </field>
3155 <field>
3156 <name>SETUP_TOKEN</name>
3157 <position>2</position>
3158 </field>
3159 <field>
3160 <name>SOF</name>
3161 <position>1</position>
3162 </field>
3163 <field>
3164 <name>SETUP_DATA</name>
3165 <desc>Setup data are ready to be accessed in SETUPDAT buffer.</desc>
3166 <position>0</position>
3167 </field>
3168 </register>
3169 </node>
3170 <node>
3171 <name>EPIEN</name>
3172 <instance>
3173 <name>IN04IEN</name>
3174 <address>0x194</address>
3175 </instance>
3176 <instance>
3177 <name>OUT04IEN</name>
3178 <address>0x196</address>
3179 </instance>
3180 <register>
3181 <desc>Endpoint interrupt enable register</desc>
3182 <field>
3183 <name>EP_NUM</name>
3184 <position>0</position>
3185 <width>3</width>
3186 </field>
3187 </register>
3188 </node>
3189 <node>
3190 <name>USBIEN</name>
3191 <instance>
3192 <name>USBIEN</name>
3193 <address>0x198</address>
3194 </instance>
3195 <register>
3196 <desc>General usb interrupts enable register</desc>
3197 <field>
3198 <name>HS</name>
3199 <position>5</position>
3200 </field>
3201 <field>
3202 <name>RESET</name>
3203 <position>4</position>
3204 </field>
3205 <field>
3206 <name>SUSPEND</name>
3207 <position>3</position>
3208 </field>
3209 <field>
3210 <name>SETUP_TOKEN</name>
3211 <position>2</position>
3212 </field>
3213 <field>
3214 <name>SOF</name>
3215 <position>1</position>
3216 </field>
3217 <field>
3218 <name>SETUP_DATA</name>
3219 <position>0</position>
3220 </field>
3221 </register>
3222 </node>
3223 <node>
3224 <name>IVECT</name>
3225 <instance>
3226 <name>IVECT</name>
3227 <address>0x1a0</address>
3228 </instance>
3229 <register>
3230 <desc>Interrupt vector register
3231known (guessed) values:
32320x00 - SETUP
32330x10 - RESET
32340x14 - HS
32350x28 - EPs
32360xD8 - OTG</desc>
3237 </register>
3238 </node>
3239 <node>
3240 <name>ENDPRST</name>
3241 <instance>
3242 <name>ENDPRST</name>
3243 <address>0x1a2</address>
3244 </instance>
3245 <register>
3246 <desc>Endpoint reset register</desc>
3247 <field>
3248 <name>FIFO_RESET</name>
3249 <position>6</position>
3250 </field>
3251 <field>
3252 <name>TOGGLE_RESET</name>
3253 <position>5</position>
3254 </field>
3255 <field>
3256 <name>DIR</name>
3257 <position>4</position>
3258 <enum>
3259 <name>OUT</name>
3260 <value>0x0</value>
3261 </enum>
3262 <enum>
3263 <name>IN</name>
3264 <value>0x1</value>
3265 </enum>
3266 </field>
3267 <field>
3268 <name>EP_NUM</name>
3269 <position>0</position>
3270 <width>3</width>
3271 </field>
3272 </register>
3273 </node>
3274 <node>
3275 <name>USBCS</name>
3276 <instance>
3277 <name>USBCS</name>
3278 <address>0x1a3</address>
3279 </instance>
3280 <register>
3281 <field>
3282 <name>SOFT_CONNECT</name>
3283 <position>6</position>
3284 </field>
3285 <field>
3286 <name>SIGRESUME</name>
3287 <position>5</position>
3288 </field>
3289 <field>
3290 <name>USBSPEED</name>
3291 <position>1</position>
3292 </field>
3293 <field>
3294 <name>HCLSMODE</name>
3295 <position>0</position>
3296 </field>
3297 </register>
3298 </node>
3299 <node>
3300 <name>FIFOCTRL</name>
3301 <instance>
3302 <name>FIFOCTRL</name>
3303 <address>0x1a8</address>
3304 </instance>
3305 <register>
3306 <field>
3307 <name>CPU_ACCESS</name>
3308 <position>7</position>
3309 </field>
3310 <field>
3311 <name>DMA</name>
3312 <position>5</position>
3313 </field>
3314 <field>
3315 <name>DIR</name>
3316 <position>4</position>
3317 <enum>
3318 <name>OUT</name>
3319 <value>0x0</value>
3320 </enum>
3321 <enum>
3322 <name>IN</name>
3323 <value>0x1</value>
3324 </enum>
3325 </field>
3326 <field>
3327 <name>EP_NUM</name>
3328 <position>0</position>
3329 <width>3</width>
3330 </field>
3331 </register>
3332 </node>
3333 <node>
3334 <name>OTGIRQ</name>
3335 <instance>
3336 <name>OTGIRQ</name>
3337 <address>0x1bc</address>
3338 </instance>
3339 <register>
3340 <field>
3341 <name>PERIPH</name>
3342 <position>4</position>
3343 </field>
3344 <field>
3345 <name>VBUSERR</name>
3346 <position>3</position>
3347 </field>
3348 <field>
3349 <name>LOCSOFT</name>
3350 <position>2</position>
3351 </field>
3352 <field>
3353 <name>SPRDET</name>
3354 <position>1</position>
3355 </field>
3356 <field>
3357 <name>OTG_IDLE</name>
3358 <position>0</position>
3359 </field>
3360 </register>
3361 </node>
3362 <node>
3363 <name>OTGSTATUS</name>
3364 <instance>
3365 <name>OTGSTATUS</name>
3366 <address>0x1bf</address>
3367 </instance>
3368 <register/>
3369 </node>
3370 <node>
3371 <name>OTGIEN</name>
3372 <instance>
3373 <name>OTGIEN</name>
3374 <address>0x1c0</address>
3375 </instance>
3376 <register>
3377 <desc>OTG interrupt enable register</desc>
3378 </register>
3379 </node>
3380 <node>
3381 <name>HCMAXPCKL</name>
3382 <instance>
3383 <name>HCIN1MAXPCKL</name>
3384 <address>0x1e2</address>
3385 </instance>
3386 <instance>
3387 <name>HCOUT2MAXPCKL</name>
3388 <address>0x3e4</address>
3389 </instance>
3390 <register>
3391 <desc>High speed max packed size LSB</desc>
3392 </register>
3393 </node>
3394 <node>
3395 <name>STADDR</name>
3396 <instance>
3397 <name>OUT1STADDR</name>
3398 <address>0x304</address>
3399 </instance>
3400 <instance>
3401 <name>IN2STADDR</name>
3402 <address>0x348</address>
3403 </instance>
3404 <register>
3405 <desc>Endpoint buffer start address</desc>
3406 </register>
3407 </node>
3408 <node>
3409 <name>USBEIRQ</name>
3410 <instance>
3411 <name>USBEIRQ</name>
3412 <address>0x400</address>
3413 </instance>
3414 <register>
3415 <desc>USB extended irq register</desc>
3416 <field>
3417 <name>USB</name>
3418 <position>7</position>
3419 </field>
3420 <field>
3421 <name>WAKEUP</name>
3422 <position>6</position>
3423 </field>
3424 <field>
3425 <name>RESUME</name>
3426 <position>5</position>
3427 </field>
3428 <field>
3429 <name>CONDISCON</name>
3430 <position>4</position>
3431 </field>
3432 <field>
3433 <name>USBIEN</name>
3434 <position>3</position>
3435 </field>
3436 <field>
3437 <name>WAKEUPIEN</name>
3438 <position>2</position>
3439 </field>
3440 <field>
3441 <name>RESUMEIEN</name>
3442 <position>1</position>
3443 </field>
3444 <field>
3445 <name>CONDISCONIEN</name>
3446 <position>0</position>
3447 </field>
3448 </register>
3449 </node>
3450 <node>
3451 <name>USBERST</name>
3452 <instance>
3453 <name>USBERST</name>
3454 <address>0x404</address>
3455 </instance>
3456 <register/>
3457 </node>
3458 <node>
3459 <name>DMAEPSEL</name>
3460 <instance>
3461 <name>DMAEPSEL</name>
3462 <address>0x40c</address>
3463 </instance>
3464 <register>
3465 <field>
3466 <name>EP_SEL</name>
3467 <position>0</position>
3468 <width>32</width>
3469 <enum>
3470 <name>UNKNOWN</name>
3471 <value>0x0</value>
3472 </enum>
3473 <enum>
3474 <name>EP1_IN</name>
3475 <value>0x1</value>
3476 </enum>
3477 <enum>
3478 <name>EP1_OUT</name>
3479 <value>0x3</value>
3480 </enum>
3481 <enum>
3482 <name>EP2_IN</name>
3483 <value>0x4</value>
3484 </enum>
3485 <enum>
3486 <name>EP2_OUT</name>
3487 <value>0xc</value>
3488 </enum>
3489 </field>
3490 </register>
3491 </node>
3492 </node>
3493 <node>
3494 <name>YUV2RGB</name>
3495 <title>Color Space Conversion Accelerator</title>
3496 <instance>
3497 <name>YUV2RGB</name>
3498 <address>0xb00f0000</address>
3499 </instance>
3500 <node>
3501 <name>CTL</name>
3502 <instance>
3503 <name>CTL</name>
3504 <address>0x0</address>
3505 </instance>
3506 <register>
3507 <field>
3508 <name>RESERVED</name>
3509 <position>22</position>
3510 <width>10</width>
3511 </field>
3512 <field>
3513 <name>RFBM</name>
3514 <desc>Read fifo block mode.</desc>
3515 <position>21</position>
3516 </field>
3517 <field>
3518 <name>WFBM</name>
3519 <desc>Write fifo block mode</desc>
3520 <position>20</position>
3521 </field>
3522 <field>
3523 <name>EN</name>
3524 <desc>RGB Decoder enable.</desc>
3525 <position>19</position>
3526 </field>
3527 <field>
3528 <name>FES</name>
3529 <desc>Fifo empty status.</desc>
3530 <position>18</position>
3531 </field>
3532 <field>
3533 <name>WDCS</name>
3534 <desc>Write Data/Command Select</desc>
3535 <position>16</position>
3536 <width>2</width>
3537 <enum>
3538 <name>CMD</name>
3539 <desc>Write LCD register address</desc>
3540 <value>0x0</value>
3541 </enum>
3542 <enum>
3543 <name>DATA</name>
3544 <desc>Write LCD register data</desc>
3545 <value>0x1</value>
3546 </enum>
3547 <enum>
3548 <name>RGB</name>
3549 <desc>RGB565 Data FrameBuffer Transfer</desc>
3550 <value>0x2</value>
3551 </enum>
3552 <enum>
3553 <name>YUV</name>
3554 <desc>YCbCr/YUV Data FrameBuffer Transfer</desc>
3555 <value>0x3</value>
3556 </enum>
3557 </field>
3558 <field>
3559 <name>DEST</name>
3560 <desc>RGB Decoder Destination.</desc>
3561 <position>15</position>
3562 </field>
3563 <field>
3564 <name>FORMATS</name>
3565 <desc>RGB Format</desc>
3566 <position>11</position>
3567 <width>3</width>
3568 <enum>
3569 <name>RGB565_1</name>
3570 <desc>16bit (RGB 565 1transfer)</desc>
3571 <value>0x0</value>
3572 </enum>
3573 <enum>
3574 <name>RGB666_1</name>
3575 <desc>18bit (RGB 666 1transfer)</desc>
3576 <value>0x1</value>
3577 </enum>
3578 <enum>
3579 <name>RGB565_2</name>
3580 <desc>8bit (RGB 565 2transfers)</desc>
3581 <value>0x2</value>
3582 </enum>
3583 <enum>
3584 <name>RGB666_2</name>
3585 <desc>9bit (RGB 666 2transfers)</desc>
3586 <value>0x3</value>
3587 </enum>
3588 <enum>
3589 <name>RGB888_3</name>
3590 <desc>8bit (RGB 888 3transfers)</desc>
3591 <value>0x4</value>
3592 </enum>
3593 <enum>
3594 <name>RGB666_3</name>
3595 <desc>6bit (RGB 666 3transfers)</desc>
3596 <value>0x5</value>
3597 </enum>
3598 </field>
3599 <field>
3600 <name>SEQ</name>
3601 <desc>RGB Sequence</desc>
3602 <position>10</position>
3603 <enum>
3604 <name>RGB</name>
3605 <value>0x0</value>
3606 </enum>
3607 <enum>
3608 <name>BGR</name>
3609 <value>0x1</value>
3610 </enum>
3611 </field>
3612 <field>
3613 <name>FWCS</name>
3614 <desc>FIFO write channel select.</desc>
3615 <position>9</position>
3616 <enum>
3617 <name>SPECIAL</name>
3618 <value>0x0</value>
3619 </enum>
3620 <enum>
3621 <name>AHB</name>
3622 <value>0x1</value>
3623 </enum>
3624 </field>
3625 <field>
3626 <name>FRCS</name>
3627 <desc>FIFO read channel select</desc>
3628 <position>8</position>
3629 <enum>
3630 <name>SPECIAL</name>
3631 <value>0x0</value>
3632 </enum>
3633 <enum>
3634 <name>AHB</name>
3635 <value>0x1</value>
3636 </enum>
3637 </field>
3638 <field>
3639 <name>EMDE</name>
3640 <desc>FIFO Empty (Write) DRQ Enable.</desc>
3641 <position>7</position>
3642 </field>
3643 <field>
3644 <name>EMIE</name>
3645 <desc>FIFO Empty (Write) IRQ Enable.</desc>
3646 <position>6</position>
3647 </field>
3648 <field>
3649 <name>FUDE</name>
3650 <desc>FIFO Full (Read) DRQ Enable.</desc>
3651 <position>5</position>
3652 </field>
3653 <field>
3654 <name>FUIE</name>
3655 <desc>FIFO Full (Read) IRQ Enable.</desc>
3656 <position>4</position>
3657 </field>
3658 <field>
3659 <name>EMCO</name>
3660 <desc>FIFO Empty (Write) Condition.</desc>
3661 <position>3</position>
3662 <enum>
3663 <name>EMPTY_4_8</name>
3664 <value>0x0</value>
3665 </enum>
3666 <enum>
3667 <name>EMPTY_0_8</name>
3668 <value>0x1</value>
3669 </enum>
3670 </field>
3671 <field>
3672 <name>EMIP</name>
3673 <desc>FIFO Empty (Write) IRQ Pending Bit.</desc>
3674 <position>2</position>
3675 </field>
3676 <field>
3677 <name>FUIP</name>
3678 <desc>FIFO Full (Read) IRQ Pending Bit.</desc>
3679 <position>1</position>
3680 </field>
3681 <field>
3682 <name>ERP</name>
3683 <desc>FIFO Error Pending Bit. Write 1 to the bit to clear it and reset the FIFO.</desc>
3684 <position>0</position>
3685 </field>
3686 </register>
3687 </node>
3688 <node>
3689 <name>FIFODATA</name>
3690 <instance>
3691 <name>FIFODATA</name>
3692 <address>0x4</address>
3693 </instance>
3694 <register/>
3695 </node>
3696 <node>
3697 <name>CLKCTL</name>
3698 <instance>
3699 <name>CLKCTL</name>
3700 <address>0x8</address>
3701 </instance>
3702 <register/>
3703 </node>
3704 <node>
3705 <name>FRAMECOUNT</name>
3706 <instance>
3707 <name>FRAMECOUNT</name>
3708 <address>0xc</address>
3709 </instance>
3710 <register/>
3711 </node>
3712 </node>
1102</soc> 3713</soc>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-17 22:40:47 +0000