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authorFrank Gevaerts <frank@gevaerts.be>2008-09-17 18:50:18 +0000
committerFrank Gevaerts <frank@gevaerts.be>2008-09-17 18:50:18 +0000
commit0a584fb06cfd5defd1836d580508a08c8aa35cf0 (patch)
treee34878c2fc18d4631616cf1a2c7f57b5e67038c3
parent67def0b18c0fdb844aaac76fb3e0c52a83f1ab98 (diff)
downloadrockbox-0a584fb06cfd5defd1836d580508a08c8aa35cf0.tar.gz
rockbox-0a584fb06cfd5defd1836d580508a08c8aa35cf0.zip
annotate init sequence
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18539 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/target/arm/s5l8700/meizu-m6sl/lcd-m6sl.c91
1 files changed, 48 insertions, 43 deletions
diff --git a/firmware/target/arm/s5l8700/meizu-m6sl/lcd-m6sl.c b/firmware/target/arm/s5l8700/meizu-m6sl/lcd-m6sl.c
index dac0dc6164..e6e14b5e57 100644
--- a/firmware/target/arm/s5l8700/meizu-m6sl/lcd-m6sl.c
+++ b/firmware/target/arm/s5l8700/meizu-m6sl/lcd-m6sl.c
@@ -171,47 +171,74 @@ void lcd_set_flip(bool yesno)
171} 171}
172 172
173 173
174
175void lcd_off(void)
176{
177 switch(controller_type)
178 {
179 case 0x0154:
180 spi_set_reg(S6D0154_REG_DISPLAY_CONTROL, 0x12);
181 delay(20);
182 spi_set_reg(S6D0154_REG_DISPLAY_CONTROL, 0x00);
183 break;
184 }
185}
186
187void lcd_on(void)
188{
189 switch(controller_type)
190 {
191 case 0x0154:
192 spi_set_reg(S6D0154_REG_DISPLAY_CONTROL, 0x12);
193 delay(20);
194 spi_set_reg(S6D0154_REG_DISPLAY_CONTROL, 0x13);
195 break;
196 }
197}
174/* LCD init */ 198/* LCD init */
175void lcd_init_device(void) 199void lcd_init_device(void)
176{ 200{
201 init_lcd_spi();
177 controller_type = lcd_read_id(); 202 controller_type = lcd_read_id();
178 switch(controller_type) 203 switch(controller_type)
179 { 204 {
180 case 0x0154: 205 case 0x0154:
181 spi_set_reg(S6D0154_REG_EXTERNAL_INTERFACE_CONTROL, 0x130); 206 spi_set_reg(S6D0154_REG_EXTERNAL_INTERFACE_CONTROL, 0x130); // RGB interface, RGB interface for PNP mode
182 spi_set_reg(S6D0154_REG_MTP_TEST_KEY, 0x8d); 207 spi_set_reg(S6D0154_REG_MTP_TEST_KEY, 0x8d); // ??
183 spi_set_reg(0x92, 0x10); 208 spi_set_reg(0x92, 0x10);
184 spi_set_reg(S6D0154_REG_POWER_CONTROL_2, 0x1b); 209 /* See also datasheet 11.3 Set up Flow of Generated Power Supply */
185 spi_set_reg(S6D0154_REG_POWER_CONTROL_3, 0x3101); 210 spi_set_reg(S6D0154_REG_POWER_CONTROL_2, 0x1b); // VC1IEN, 2.76V
186 spi_set_reg(S6D0154_REG_POWER_CONTROL_4, 0x105f); 211 spi_set_reg(S6D0154_REG_POWER_CONTROL_3, 0x3101);// VGH=6*VCI1, VGL=-4*VCI1, f(DCCLK):f(DCCLK1)=1:0.5, f(DCCLK) : f(DCCLK3)= 1:0.5
212 spi_set_reg(S6D0154_REG_POWER_CONTROL_4, 0x105f);//DCR_EX=1(Use dotclock)
187 spi_set_reg(S6D0154_REG_POWER_CONTROL_5, 0x667f); 213 spi_set_reg(S6D0154_REG_POWER_CONTROL_5, 0x667f);
188 spi_set_reg(S6D0154_REG_POWER_CONTROL_1, 0x800); 214 spi_set_reg(S6D0154_REG_POWER_CONTROL_1, 0x800);
189 delay(20); 215 delay(20); // >10ms
190 spi_set_reg(S6D0154_REG_POWER_CONTROL_2, 0x11b); 216 spi_set_reg(S6D0154_REG_POWER_CONTROL_2, 0x11b);
191 delay(20); 217 delay(20); // >10ms
192 spi_set_reg(S6D0154_REG_POWER_CONTROL_2, 0x31b); 218 spi_set_reg(S6D0154_REG_POWER_CONTROL_2, 0x31b);
193 delay(20); 219 delay(20); // >10ms
194 spi_set_reg(S6D0154_REG_POWER_CONTROL_2, 0x71b); 220 spi_set_reg(S6D0154_REG_POWER_CONTROL_2, 0x71b);
195 delay(20); 221 delay(20); // >10ms
196 spi_set_reg(S6D0154_REG_POWER_CONTROL_2, 0xf1b); 222 spi_set_reg(S6D0154_REG_POWER_CONTROL_2, 0xf1b);
197 delay(20); 223 delay(20); // >10ms
198 spi_set_reg(S6D0154_REG_POWER_CONTROL_2, 0xf3b); 224 spi_set_reg(S6D0154_REG_POWER_CONTROL_2, 0xf3b);
199 delay(20); 225 delay(30); // >30ms
200 spi_set_reg(S6D0154_REG_DRIVER_OUTPUT_CONTROL, 0x2128); 226 spi_set_reg(S6D0154_REG_DRIVER_OUTPUT_CONTROL, 0x2128);
201 spi_set_reg(S6D0154_REG_LCD_DRIVING_WAVEFORM_CONTROL, 0x100); 227 spi_set_reg(S6D0154_REG_LCD_DRIVING_WAVEFORM_CONTROL, 0x100);
202 spi_set_reg(S6D0154_REG_ENTRY_MODE, 0x1030); 228 spi_set_reg(S6D0154_REG_ENTRY_MODE, 0x1030);//{DB [17:12], DB [11:6], DB [5:0]} is assigned to {B, G, R}. Horizontal first, auto increment address, write from 0x0000 to 0xdbaf
203 spi_set_reg(S6D0154_REG_DISPLAY_CONTROL, 0); 229 spi_set_reg(S6D0154_REG_DISPLAY_CONTROL, 0); // all off
204 spi_set_reg(S6D0154_REG_BLANK_PERIOD_CONTROL, 0x808); 230 spi_set_reg(S6D0154_REG_BLANK_PERIOD_CONTROL, 0x808);
205 spi_set_reg(S6D0154_REG_FRAME_CYCLE_CONTROL, 0x1100); 231 spi_set_reg(S6D0154_REG_FRAME_CYCLE_CONTROL, 0x1100);
206 spi_set_reg(S6D0154_REG_START_OSCILLATION, 0xf01); 232 spi_set_reg(S6D0154_REG_START_OSCILLATION, 0xf01);// Start oscillator, X 1.25
207 spi_set_reg(S6D0154_REG_VCI_RECYCLING, 0); 233 spi_set_reg(S6D0154_REG_VCI_RECYCLING, 0);
208 spi_set_reg(S6D0154_REG_GATE_SCAN_POSITION, 0); 234 spi_set_reg(S6D0154_REG_GATE_SCAN_POSITION, 0);
209 spi_set_reg(S6D0154_REG_PARTIAL_SCREEN_DRIVING_POSITION_1, 0x13f); 235 /* Set things up to write to the entire screen */
210 spi_set_reg(S6D0154_REG_PARTIAL_SCREEN_DRIVING_POSITION_2, 0); 236 spi_set_reg(S6D0154_REG_PARTIAL_SCREEN_DRIVING_POSITION_1, 319); // end of partial screen
211 spi_set_reg(S6D0154_REG_HORIZONTAL_WINDOW_ADDRESS_1, 0xef); 237 spi_set_reg(S6D0154_REG_PARTIAL_SCREEN_DRIVING_POSITION_2, 0); // start of partial screen
212 spi_set_reg(S6D0154_REG_HORIZONTAL_WINDOW_ADDRESS_2, 0); 238 spi_set_reg(S6D0154_REG_HORIZONTAL_WINDOW_ADDRESS_1, 239); // end of window
213 spi_set_reg(S6D0154_REG_VERTICAL_WINDOW_ADDRESS_1, 0x13f); 239 spi_set_reg(S6D0154_REG_HORIZONTAL_WINDOW_ADDRESS_2, 0); // start of window
214 spi_set_reg(S6D0154_REG_VERTICAL_WINDOW_ADDRESS_2, 0); 240 spi_set_reg(S6D0154_REG_VERTICAL_WINDOW_ADDRESS_1, 319); // end of window
241 spi_set_reg(S6D0154_REG_VERTICAL_WINDOW_ADDRESS_2, 0); // start of window
215 spi_set_reg(S6D0154_REG_GAMMA_CONTROL_1, 0); 242 spi_set_reg(S6D0154_REG_GAMMA_CONTROL_1, 0);
216 spi_set_reg(S6D0154_REG_GAMMA_CONTROL_2, 0xf00); 243 spi_set_reg(S6D0154_REG_GAMMA_CONTROL_2, 0xf00);
217 spi_set_reg(S6D0154_REG_GAMMA_CONTROL_3, 0xa03); 244 spi_set_reg(S6D0154_REG_GAMMA_CONTROL_3, 0xa03);
@@ -222,34 +249,12 @@ void lcd_init_device(void)
222 spi_set_reg(S6D0154_REG_GAMMA_CONTROL_8, 3); 249 spi_set_reg(S6D0154_REG_GAMMA_CONTROL_8, 3);
223 spi_set_reg(S6D0154_REG_GAMMA_CONTROL_9, 0x1f07); 250 spi_set_reg(S6D0154_REG_GAMMA_CONTROL_9, 0x1f07);
224 spi_set_reg(S6D0154_REG_GAMMA_CONTROL_10, 0x71f); 251 spi_set_reg(S6D0154_REG_GAMMA_CONTROL_10, 0x71f);
225 break;
226 }
227}
228
229
230void lcd_off(void)
231{
232 switch(controller_type)
233 {
234 case 0x0154:
235 spi_set_reg(S6D0154_REG_DISPLAY_CONTROL, 0x12);
236 delay(20); 252 delay(20);
237 spi_set_reg(S6D0154_REG_DISPLAY_CONTROL, 0x00); 253 lcd_on();
238 break; 254 break;
239 } 255 }
240} 256}
241 257
242void lcd_on(void)
243{
244 switch(controller_type)
245 {
246 case 0x0154:
247 spi_set_reg(S6D0154_REG_DISPLAY_CONTROL, 0x12);
248 delay(20);
249 spi_set_reg(S6D0154_REG_DISPLAY_CONTROL, 0x13);
250 break;
251 }
252}
253 258
254/*** Update functions ***/ 259/*** Update functions ***/
255 260