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authorJens Arnold <amiconn@rockbox.org>2010-06-04 21:12:06 +0000
committerJens Arnold <amiconn@rockbox.org>2010-06-04 21:12:06 +0000
commit081bda8ab258c763e654067740f365be68269340 (patch)
tree6c259a698a78d16c967952c3c9fe5504e9b21bc4
parentb91fa0425090536a254e25807e75ff624c07d503 (diff)
downloadrockbox-081bda8ab258c763e654067740f365be68269340.tar.gz
rockbox-081bda8ab258c763e654067740f365be68269340.zip
Port greylib blitting optimisation to clipv1.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26557 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/target/arm/as3525/sansa-clip/lcd-as-clip.S46
1 files changed, 17 insertions, 29 deletions
diff --git a/firmware/target/arm/as3525/sansa-clip/lcd-as-clip.S b/firmware/target/arm/as3525/sansa-clip/lcd-as-clip.S
index 5a52eb032c..942ddf79f8 100644
--- a/firmware/target/arm/as3525/sansa-clip/lcd-as-clip.S
+++ b/firmware/target/arm/as3525/sansa-clip/lcd-as-clip.S
@@ -56,42 +56,30 @@ lcd_grey_data:
56 ldr lr, =DBOP_BASE 56 ldr lr, =DBOP_BASE
57 57
58.greyloop: 58.greyloop:
59 ldmia r1, {r3-r4} /* Fetch 8 pixel phases */
60 ldmia r0!, {r5-r6} /* Fetch 8 pixel values */
61 59
62 mov r7, #0 60 ldmia r1, {r3-r4}
63 61
64 /* set bits 15..12 */ 62 and r5, r12, r3 @ r5 = 3.......2.......1.......0.......
65 tst r3, #0x80 63 and r6, r12, r4 @ r6 = 7.......6.......5.......4.......
66 orrne r7, r7, #0x8000 64 orr r5, r5, r6, lsr #4 @ r5 = 3...7...2...6...1...5...0...4...
67 tst r3, #0x8000 65 orr r5, r5, r5, lsr #9 @ r5 = 3...7...23..67..12..56..01..45..
68 orrne r7, r7, #0x4000 66 orr r5, r5, r5, lsr #9 @ r5 = 3...7...23..67..123.567.012.456.
69 tst r3, #0x800000 67 orr r5, r5, r5, lsr #9 @ r5 = 3...7...23..67..123.567.01234567
70 orrne r7, r7, #0x2000 68 and r5, r5, #0xff
71 tst r3, #0x80000000 69 orr r5, r5, r5, lsl #8 @ post processing for clipv1 LCD */
72 orrne r7, r7, #0x1000 70
71 ldmia r0!, {r6-r7}
73 bic r3, r3, r12 72 bic r3, r3, r12
74 add r3, r3, r5 73 add r3, r3, r6
75
76 /* set bits 3..0 */
77 tst r4, #0x80
78 orrne r7, r7, #0x08
79 tst r4, #0x8000
80 orrne r7, r7, #0x04
81 tst r4, #0x800000
82 orrne r7, r7, #0x02
83 tst r4, #0x80000000
84 orrne r7, r7, #0x01
85 bic r4, r4, r12 74 bic r4, r4, r12
86 add r4, r4, r6 75 add r4, r4, r7
87
88 stmia r1!, {r3-r4} 76 stmia r1!, {r3-r4}
89 77
90 strh r7, [lr, #0x10] @ DBOP_DOUT 78 strh r5, [lr, #0x10] @ DBOP_DOUT
91 79
921: 801:
93 ldr r5, [lr, #0xC] @ DBOP_STAT 81 ldr r6, [lr, #0xC] @ DBOP_STAT
94 ands r5, r5, #(1<<6) @ wait until push fifo is full 82 ands r6, r6, #(1<<6) @ wait until push fifo is full
95 bne 1b 83 bne 1b
96 84
97 subs r2, r2, #1 85 subs r2, r2, #1