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author | Thom Johansen <thomj@rockbox.org> | 2005-12-12 13:21:08 +0000 |
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committer | Thom Johansen <thomj@rockbox.org> | 2005-12-12 13:21:08 +0000 |
commit | 07a2ad2a2246c649ec86c2adb077ec9ed3cfef11 (patch) | |
tree | 202e112338355fcc8d2e2a2eaad8438237b0c158 | |
parent | 40729e902b4e0d6b8b6fdd7e5f9108dcab46ba96 (diff) | |
download | rockbox-07a2ad2a2246c649ec86c2adb077ec9ed3cfef11.tar.gz rockbox-07a2ad2a2246c649ec86c2adb077ec9ed3cfef11.zip |
Basic exceptions support for iPod and ARM targets. SDRAM for iPod targets remapped to base address 0 to facilitate. Changed some crt0.S #ifdefs to allow for code resuse on other ARM targets.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@8223 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/app.lds | 2 | ||||
-rw-r--r-- | firmware/crt0.S | 145 |
2 files changed, 127 insertions, 20 deletions
diff --git a/firmware/app.lds b/firmware/app.lds index af5cd8d9da..e17e5a97b9 100644 --- a/firmware/app.lds +++ b/firmware/app.lds | |||
@@ -123,7 +123,7 @@ _pluginbuf = 0; | |||
123 | #define IRAMORIG 0x10000000 | 123 | #define IRAMORIG 0x10000000 |
124 | #define IRAMSIZE 0xc000 | 124 | #define IRAMSIZE 0xc000 |
125 | #elif CONFIG_CPU==PP5020 | 125 | #elif CONFIG_CPU==PP5020 |
126 | #define DRAMORIG 0x10000000 + STUBOFFSET | 126 | #define DRAMORIG 0x00000000 + STUBOFFSET |
127 | #define IRAMORIG 0x40000000 | 127 | #define IRAMORIG 0x40000000 |
128 | #define IRAMSIZE 0xc000 | 128 | #define IRAMSIZE 0xc000 |
129 | #else | 129 | #else |
diff --git a/firmware/crt0.S b/firmware/crt0.S index 82f1b82a73..bb772e2c5d 100644 --- a/firmware/crt0.S +++ b/firmware/crt0.S | |||
@@ -19,29 +19,79 @@ | |||
19 | #include "config.h" | 19 | #include "config.h" |
20 | #include "cpu.h" | 20 | #include "cpu.h" |
21 | 21 | ||
22 | #if (CONFIG_CPU == PP5002) || (CONFIG_CPU == PP5020) | 22 | #if defined(CPU_ARM) |
23 | .section .init.text,"ax",%progbits | 23 | .section .init.text,"ax",%progbits |
24 | #else | 24 | #else |
25 | .section .init.text,"ax",@progbits | 25 | .section .init.text,"ax",@progbits |
26 | #endif | 26 | #endif |
27 | |||
27 | .global start | 28 | .global start |
28 | start: | 29 | start: |
29 | #if (CONFIG_CPU == PP5002) || (CONFIG_CPU == PP5020) | ||
30 | 30 | ||
31 | /* Based on startup.s from the iPodLinux loader | 31 | #if defined(CPU_ARM) |
32 | |||
33 | /* iPod bootloader and startup code based on startup.s from the iPodLinux loader | ||
32 | * | 34 | * |
33 | * Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org) | 35 | * Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org) |
34 | * Copyright (c) 2005, Bernard Leach <leachbj@bouncycastle.org> | 36 | * Copyright (c) 2005, Bernard Leach <leachbj@bouncycastle.org> |
35 | * | 37 | * |
36 | */ | 38 | */ |
37 | .equ PP5002_PROC_ID, 0xc4000000 | ||
38 | .equ PP5002_COP_CTRL, 0xcf004058 | ||
39 | .equ PP5020_PROC_ID, 0x60000000 | ||
40 | .equ PP5020_COP_CTRL, 0x60007004 | ||
41 | 39 | ||
42 | start: | ||
43 | #ifndef BOOTLOADER | 40 | #ifndef BOOTLOADER |
44 | /* Zero out IBSS */ | 41 | #if CONFIG_CPU == PP5002 || CONFIG_CPU == PP5020 |
42 | b pad_skip | ||
43 | .space 50*4 /* (more than enough) space for exception vectors */ | ||
44 | pad_skip: | ||
45 | /* We need to remap memory from wherever SDRAM is mapped natively, to | ||
46 | base address 0, so we can put our exception vectors there. We don't | ||
47 | want to do this remapping while executing from SDRAM, so we copy the | ||
48 | remapping code to IRAM, then execute from there. Hence, the following | ||
49 | code is compiled for address 0, but is currently executing at either | ||
50 | 0x28000000 or 0x10000000, depending on chipset version. Do not use any | ||
51 | absolute addresses until remapping has been done. */ | ||
52 | ldr r1, =0x40000000 | ||
53 | ldr r2, =remap_start | ||
54 | ldr r3, =remap_end | ||
55 | |||
56 | and r5, pc, #0xff000000 /* adjust for execute address */ | ||
57 | orr r2, r2, r5 | ||
58 | orr r3, r3, r5 | ||
59 | |||
60 | /* copy the code to 0x40000000 */ | ||
61 | 1: | ||
62 | ldr r4, [r2], #4 | ||
63 | str r4, [r1], #4 | ||
64 | cmp r2, r3 | ||
65 | ble 1b | ||
66 | |||
67 | ldr r3, =0x3f84 /* r3 and r1 values here are magic, don't touch */ | ||
68 | orr r3, r3, r5 /* adjust for execute address */ | ||
69 | ldr r2, =0xf000f014 | ||
70 | mov r1, #0x3a00 | ||
71 | ldr r0, =0xf000f010 | ||
72 | ldr r4, =0x40000000 | ||
73 | mov pc, r4 | ||
74 | |||
75 | remap_start: | ||
76 | str r1, [r0] | ||
77 | str r3, [r2] | ||
78 | ldr r0, L_post_remap | ||
79 | mov pc, r0 | ||
80 | L_post_remap: .word remap_end | ||
81 | remap_end: | ||
82 | #endif /* PP specific */ | ||
83 | |||
84 | /* Copy exception handler code to address 0 */ | ||
85 | ldr r2, =ecode | ||
86 | ldr r3, =ecodeend | ||
87 | mov r4, #0 | ||
88 | 1: | ||
89 | cmp r3, r2 | ||
90 | ldrhi r5, [r2], #4 | ||
91 | strhi r5, [r4], #4 | ||
92 | bhi 1b | ||
93 | |||
94 | /* Zero out IBSS */ | ||
45 | ldr r2, =_iedata | 95 | ldr r2, =_iedata |
46 | ldr r3, =_iend | 96 | ldr r3, =_iend |
47 | mov r4, #0 | 97 | mov r4, #0 |
@@ -50,7 +100,7 @@ start: | |||
50 | strhi r4, [r2], #4 | 100 | strhi r4, [r2], #4 |
51 | bhi 1b | 101 | bhi 1b |
52 | 102 | ||
53 | /* Copy the IRAM */ | 103 | /* Copy the IRAM */ |
54 | ldr r2, =_iramcopy | 104 | ldr r2, =_iramcopy |
55 | ldr r3, =_iramstart | 105 | ldr r3, =_iramstart |
56 | ldr r4, =_iramend | 106 | ldr r4, =_iramend |
@@ -59,7 +109,7 @@ start: | |||
59 | ldrhi r5, [r2], #4 | 109 | ldrhi r5, [r2], #4 |
60 | strhi r5, [r3], #4 | 110 | strhi r5, [r3], #4 |
61 | bhi 1b | 111 | bhi 1b |
62 | #endif | 112 | #endif /* !BOOTLOADER */ |
63 | 113 | ||
64 | /* Initialise bss section to zero */ | 114 | /* Initialise bss section to zero */ |
65 | ldr r2, =_edata | 115 | ldr r2, =_edata |
@@ -81,6 +131,11 @@ start: | |||
81 | bhi 1b | 131 | bhi 1b |
82 | 132 | ||
83 | #ifdef BOOTLOADER | 133 | #ifdef BOOTLOADER |
134 | #if CONFIG_CPU == PP5002 || CONFIG_CPU == PP5020 | ||
135 | .equ PP5002_PROC_ID, 0xc4000000 | ||
136 | .equ PP5002_COP_CTRL, 0xcf004058 | ||
137 | .equ PP5020_PROC_ID, 0x60000000 | ||
138 | .equ PP5020_COP_CTRL, 0x60007004 | ||
84 | /* TODO: the high part of the address is probably dependent on CONFIG_CPU. | 139 | /* TODO: the high part of the address is probably dependent on CONFIG_CPU. |
85 | Since we tend to use ifdefs for each chipset target | 140 | Since we tend to use ifdefs for each chipset target |
86 | anyway, we might as well just hardcode it here. | 141 | anyway, we might as well just hardcode it here. |
@@ -146,6 +201,8 @@ start_loc: | |||
146 | ldr r1, =startup_loc | 201 | ldr r1, =startup_loc |
147 | str r0, [r1] | 202 | str r0, [r1] |
148 | 203 | ||
204 | #if 0 | ||
205 | /* TODO: fix something for the COP to wake up to, until then let it sleep. */ | ||
149 | #if CONFIG_CPU==PP5002 | 206 | #if CONFIG_CPU==PP5002 |
150 | /* make sure COP is sleeping */ | 207 | /* make sure COP is sleeping */ |
151 | ldr r4, =0xcf004050 | 208 | ldr r4, =0xcf004050 |
@@ -167,11 +224,11 @@ start_loc: | |||
167 | beq 1b | 224 | beq 1b |
168 | 225 | ||
169 | /* wake up COP */ | 226 | /* wake up COP */ |
170 | @ ldr r4, =PP5020_COP_CTRL | 227 | @ldr r4, =PP5020_COP_CTRL |
171 | mov r3, #0x0 | 228 | mov r3, #0x0 |
172 | str r3, [r4] | 229 | str r3, [r4] |
173 | #endif | 230 | #endif |
174 | 231 | #endif | |
175 | /* jump to start location */ | 232 | /* jump to start location */ |
176 | mov pc, r0 | 233 | mov pc, r0 |
177 | 234 | ||
@@ -183,11 +240,61 @@ startup_loc: | |||
183 | boot_table: | 240 | boot_table: |
184 | /* here comes the boot table, don't move its offset */ | 241 | /* here comes the boot table, don't move its offset */ |
185 | .space 400 | 242 | .space 400 |
186 | #else | 243 | #endif /* PP specific */ |
187 | /* Non-bootloader startup code */ | 244 | /* Code for ARM bootloader targets other than iPod go here */ |
188 | ldr r0, =main | 245 | #else /* BOOTLOADER */ |
189 | mov pc, r0 | 246 | |
190 | #endif /* BOOTLOADER (iPod) */ | 247 | /* Set up stack for IRQ mode */ |
248 | msr cpsr_c, #0xd2 | ||
249 | ldr sp, =irq_stack | ||
250 | /* Switch to supervisor mode, enable IRQ and FIQ processing */ | ||
251 | msr cpsr_c, #0x13 | ||
252 | ldr sp, =stackend | ||
253 | bl main | ||
254 | /* main() should never return */ | ||
255 | |||
256 | /* Exception handlers. Will be copied to address 0 after memory remapping */ | ||
257 | ecode: | ||
258 | ldr pc, [pc, #24] | ||
259 | ldr pc, [pc, #24] | ||
260 | ldr pc, [pc, #24] | ||
261 | ldr pc, [pc, #24] | ||
262 | ldr pc, [pc, #24] | ||
263 | ldr pc, [pc, #24] | ||
264 | ldr pc, [pc, #24] | ||
265 | ldr pc, [pc, #24] | ||
266 | |||
267 | /* Exception vectors */ | ||
268 | .word start | ||
269 | .word undef_instr_handler | ||
270 | .word software_int_handler | ||
271 | .word prefetch_abort_handler | ||
272 | .word data_abort_handler | ||
273 | .word reserved_handler | ||
274 | .word irq_handler | ||
275 | .word fiq_handler | ||
276 | ecodeend: | ||
277 | |||
278 | undef_instr_handler: | ||
279 | software_int_handler: | ||
280 | reserved_handler: | ||
281 | movs pc, lr | ||
282 | |||
283 | prefetch_abort_handler: | ||
284 | fiq_handler: | ||
285 | subs pc, lr, #4 | ||
286 | |||
287 | data_abort_handler: | ||
288 | subs pc, lr, #8 | ||
289 | |||
290 | irq_handler: | ||
291 | subs pc, lr, #4 | ||
292 | |||
293 | /* 256 words of IRQ stack */ | ||
294 | .space 256*4 | ||
295 | irq_stack: | ||
296 | |||
297 | #endif /* BOOTLOADER */ | ||
191 | 298 | ||
192 | #elif CONFIG_CPU == TCC730 | 299 | #elif CONFIG_CPU == TCC730 |
193 | /* Platform: Gmini 120/SP */ | 300 | /* Platform: Gmini 120/SP */ |