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author | Jack Halpin <jack.halpin@gmail.com> | 2009-10-26 07:06:37 +0000 |
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committer | Jack Halpin <jack.halpin@gmail.com> | 2009-10-26 07:06:37 +0000 |
commit | 03986d4ec73a5d1a03f35f250212420866f309a4 (patch) | |
tree | 5418a00e187b53118dac52e648916c12a02491b9 | |
parent | 17d7f023b724d1ddb8f5e3388318ea6a1c98d707 (diff) | |
download | rockbox-03986d4ec73a5d1a03f35f250212420866f309a4.tar.gz rockbox-03986d4ec73a5d1a03f35f250212420866f309a4.zip |
Revert r23350 "AMS Sansa: Assume IDECLK is MCLK for the internal SD Disk."
More information makes this assumption seem incorrect.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23356 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/target/arm/as3525/ata_sd_as3525.c | 18 | ||||
-rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 7 | ||||
-rw-r--r-- | firmware/target/arm/as3525/debug-as3525.c | 10 |
3 files changed, 13 insertions, 22 deletions
diff --git a/firmware/target/arm/as3525/ata_sd_as3525.c b/firmware/target/arm/as3525/ata_sd_as3525.c index 7567ac498d..65df027c30 100644 --- a/firmware/target/arm/as3525/ata_sd_as3525.c +++ b/firmware/target/arm/as3525/ata_sd_as3525.c | |||
@@ -103,17 +103,9 @@ static void init_pl180_controller(const int drive); | |||
103 | 103 | ||
104 | static tCardInfo card_info[NUM_DRIVES]; | 104 | static tCardInfo card_info[NUM_DRIVES]; |
105 | 105 | ||
106 | #ifdef HAVE_MULTIDRIVE | 106 | /* maximum timeouts recommanded in the SD Specification v2.00 */ |
107 | /* maximum timeouts recommended in the SD Specification v2.00 */ | 107 | #define SD_MAX_READ_TIMEOUT ((AS3525_PCLK_FREQ) / 1000 * 100) /* 100 ms */ |
108 | #define SD_MAX_READ_TIMEOUT (((drive == SD_SLOT_AS3525)? (AS3525_PCLK_FREQ): \ | 108 | #define SD_MAX_WRITE_TIMEOUT ((AS3525_PCLK_FREQ) / 1000 * 250) /* 250 ms */ |
109 | (AS3525_IDE_FREQ)) / 1000 * 100) /* 100 ms */ | ||
110 | #define SD_MAX_WRITE_TIMEOUT (((drive == SD_SLOT_AS3525)? (AS3525_PCLK_FREQ): \ | ||
111 | (AS3525_IDE_FREQ)) / 1000 * 250) /* 250 ms */ | ||
112 | #else | ||
113 | /* maximum timeouts recommended in the SD Specification v2.00 */ | ||
114 | #define SD_MAX_READ_TIMEOUT ((AS3525_IDE_FREQ) / 1000 * 100) /* 100 ms */ | ||
115 | #define SD_MAX_WRITE_TIMEOUT ((AS3525_IDE_FREQ) / 1000 * 250) /* 250 ms */ | ||
116 | #endif | ||
117 | 109 | ||
118 | /* for compatibility */ | 110 | /* for compatibility */ |
119 | static long last_disk_activity = -1; | 111 | static long last_disk_activity = -1; |
@@ -314,7 +306,7 @@ static int sd_init_card(const int drive) | |||
314 | /* End of Card Identification Mode ************************************/ | 306 | /* End of Card Identification Mode ************************************/ |
315 | 307 | ||
316 | 308 | ||
317 | /* full speed for controller clock MCICLK = MCLK = PCLK = IDECLK = 62 MHz */ | 309 | /* full speed for controller clock MCICLK = MCLK = PCLK = 62 MHz */ |
318 | MCI_CLOCK(drive) |= MCI_CLOCK_BYPASS; /* FIXME: 50 MHz is spec limit */ | 310 | MCI_CLOCK(drive) |= MCI_CLOCK_BYPASS; /* FIXME: 50 MHz is spec limit */ |
319 | mci_delay(); | 311 | mci_delay(); |
320 | 312 | ||
@@ -620,7 +612,7 @@ static int sd_select_bank(signed char bank) | |||
620 | DMA_PERI_SD, DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, | 612 | DMA_PERI_SD, DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, |
621 | NULL); | 613 | NULL); |
622 | 614 | ||
623 | MCI_DATA_TIMER(INTERNAL_AS3525) = ((AS3525_IDE_FREQ) / 1000 * 250) /* 250 ms */; | 615 | MCI_DATA_TIMER(INTERNAL_AS3525) = SD_MAX_WRITE_TIMEOUT; |
624 | MCI_DATA_LENGTH(INTERNAL_AS3525) = 512; | 616 | MCI_DATA_LENGTH(INTERNAL_AS3525) = 512; |
625 | MCI_DATA_CTRL(INTERNAL_AS3525) = (1<<0) /* enable */ | | 617 | MCI_DATA_CTRL(INTERNAL_AS3525) = (1<<0) /* enable */ | |
626 | (0<<1) /* transfer direction */ | | 618 | (0<<1) /* transfer direction */ | |
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 319b9f57f0..560e067510 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h | |||
@@ -113,15 +113,14 @@ | |||
113 | #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/ | 113 | #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/ |
114 | #define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ) | 114 | #define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ) |
115 | #define AS3525_I2C_FREQ 400000 | 115 | #define AS3525_I2C_FREQ 400000 |
116 | |||
117 | /* For now use same divider for ident frequencies on both internal and uSD cards */ | ||
118 | #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) | 116 | #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) |
119 | #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ | 117 | #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ |
120 | 118 | ||
121 | #define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */ | 119 | #define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */ |
122 | #define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/ | 120 | #define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/ |
123 | /* for now use IDECLK == PCLK for consistency */ | 121 | #define AS3525_IDE_FREQ 90000000 /* The OF uses 66MHz maximal freq |
124 | #define AS3525_IDE_FREQ AS3525_PCLK_FREQ /* The OF uses 66MHz maximal freq */ | 122 | but sd transfers fail on some |
123 | players with this limit */ | ||
125 | 124 | ||
126 | //#define AS3525_USB_SEL AS3525_CLK_PLLA /* Input Source */ | 125 | //#define AS3525_USB_SEL AS3525_CLK_PLLA /* Input Source */ |
127 | //#define AS3525_USB_DIV /* div = 1/(n=0?1:2n)*/ | 126 | //#define AS3525_USB_DIV /* div = 1/(n=0?1:2n)*/ |
diff --git a/firmware/target/arm/as3525/debug-as3525.c b/firmware/target/arm/as3525/debug-as3525.c index 4775278102..d8d3e013e2 100644 --- a/firmware/target/arm/as3525/debug-as3525.c +++ b/firmware/target/arm/as3525/debug-as3525.c | |||
@@ -183,9 +183,9 @@ int calc_freq(int clk) | |||
183 | if(!(MCI_NAND & (1<<8))) | 183 | if(!(MCI_NAND & (1<<8))) |
184 | return 0; | 184 | return 0; |
185 | else if(MCI_NAND & (1<<10)) | 185 | else if(MCI_NAND & (1<<10)) |
186 | return calc_freq(CLK_IDE); | 186 | return calc_freq(CLK_PCLK); |
187 | else | 187 | else |
188 | return calc_freq(CLK_IDE)/(((MCI_NAND & 0xff)+1)*2); | 188 | return calc_freq(CLK_PCLK)/(((MCI_NAND & 0xff)+1)*2); |
189 | case CLK_SD_MCLK_MSD: | 189 | case CLK_SD_MCLK_MSD: |
190 | if(!(MCI_SD & (1<<8))) | 190 | if(!(MCI_SD & (1<<8))) |
191 | return 0; | 191 | return 0; |
@@ -222,7 +222,7 @@ bool __dbg_hw_info(void) | |||
222 | { | 222 | { |
223 | int line; | 223 | int line; |
224 | int last_nand = 0; | 224 | int last_nand = 0; |
225 | #ifdef HAVE_MULTIDRIVE | 225 | #if defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_C200V2) |
226 | int last_sd = 0; | 226 | int last_sd = 0; |
227 | #endif | 227 | #endif |
228 | 228 | ||
@@ -293,10 +293,10 @@ bool __dbg_hw_info(void) | |||
293 | last_nand = MCI_NAND; | 293 | last_nand = MCI_NAND; |
294 | /* MCLK == PCLK */ | 294 | /* MCLK == PCLK */ |
295 | lcd_putsf(0, line++, "SD :%3dMHz %3dMHz", | 295 | lcd_putsf(0, line++, "SD :%3dMHz %3dMHz", |
296 | ((last_nand ? (AS3525_IDE_FREQ/ 1000000): 0) / | 296 | ((last_nand ? (AS3525_PCLK_FREQ/ 1000000): 0) / |
297 | ((last_nand & MCI_CLOCK_BYPASS)? 1:(((last_nand & 0xff)+1) * 2))), | 297 | ((last_nand & MCI_CLOCK_BYPASS)? 1:(((last_nand & 0xff)+1) * 2))), |
298 | calc_freq(CLK_SD_MCLK_NAND)/1000000); | 298 | calc_freq(CLK_SD_MCLK_NAND)/1000000); |
299 | #ifdef HAVE_MULTIDRIVE | 299 | #if defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_C200V2) |
300 | if(MCI_SD) | 300 | if(MCI_SD) |
301 | last_sd = MCI_SD; | 301 | last_sd = MCI_SD; |
302 | lcd_putsf(0, line++, "uSD :%3dMHz %3dMHz", | 302 | lcd_putsf(0, line++, "uSD :%3dMHz %3dMHz", |