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authorAidan MacDonald <amachronic@protonmail.com>2022-03-26 17:49:09 +0000
committerAidan MacDonald <amachronic@protonmail.com>2022-04-01 12:08:41 -0400
commit98f762316f0b065e9e4ce0ed8027eb0cc378eb32 (patch)
tree084b14cfd35aa60751529ef946b2e484ff11c4c5
parentde285741bfe5094d5f67b9244378359cb94b66ee (diff)
downloadrockbox-bootloader_erosq_v1.tar.gz
rockbox-bootloader_erosq_v1.zip
system: update MEM_ALIGN_ATTR for targets with CPU cachesbootloader_erosq_v1
MEM_ALIGN_ATTR should take advantage of cache line alignment on all native CPUs which define it, not just ARM CPUs. (This could arguably be done for hosted targets too, but we don't necessarily know the size of a cache line there.) Change-Id: Ife9302105ea57388afd55ce31da848b00b5b1b25
-rw-r--r--firmware/export/system.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/firmware/export/system.h b/firmware/export/system.h
index f554ac7cf1..9558be559a 100644
--- a/firmware/export/system.h
+++ b/firmware/export/system.h
@@ -307,8 +307,8 @@ static inline void cpu_boost_unlock(void)
307 307
308/* Define MEM_ALIGN_ATTR which may be used to align e.g. buffers for faster 308/* Define MEM_ALIGN_ATTR which may be used to align e.g. buffers for faster
309 * access. */ 309 * access. */
310#if defined(CPU_ARM) 310#if defined(HAVE_CPU_CACHE_ALIGN)
311 /* Use ARMs cache alignment. */ 311 /* Align to a cache line. */
312 #define MEM_ALIGN_ATTR CACHEALIGN_ATTR 312 #define MEM_ALIGN_ATTR CACHEALIGN_ATTR
313 #define MEM_ALIGN_SIZE CACHEALIGN_SIZE 313 #define MEM_ALIGN_SIZE CACHEALIGN_SIZE
314#elif defined(CPU_COLDFIRE) 314#elif defined(CPU_COLDFIRE)