From 0f701a64bee43e79f95970ae9c0ec43ea7fcdf17 Mon Sep 17 00:00:00 2001 From: Amaury Pouly Date: Sat, 6 Feb 2016 15:01:24 +0000 Subject: regtools: update v2 specification, library and tools A v2 register description file can now include register variants and instances addresses can now be a list (previously it could only be a stride or a formula). Update the library to deal with that. The convert option of swiss_knife was updated and one incompatible change was introduce: if a v1 device has several addresses, those are converted to a single v2 instance with list (instead of several single instances). This should have been the behaviour from the start. Swiss_knife can now also convert regdumps, in which case it needs to be given both the dump and register description file. Also introduce two register descriptions files (vsoc1000 and vsoc2000) which give more complicated examples of v2 register description files. Change-Id: Id9415b8363269ffaf9216abfc6dd1bd1adbfcf8d --- utils/regtools/desc/regs-example-v1.xml | 2 +- utils/regtools/desc/regs-example.xml | 153 ------------ utils/regtools/desc/regs-vsoc1000.xml | 248 ++++++++++++++++++++ utils/regtools/desc/regs-vsoc2000.xml | 396 ++++++++++++++++++++++++++++++++ utils/regtools/desc/spec-2.0.txt | 30 +++ 5 files changed, 675 insertions(+), 154 deletions(-) delete mode 100644 utils/regtools/desc/regs-example.xml create mode 100644 utils/regtools/desc/regs-vsoc1000.xml create mode 100644 utils/regtools/desc/regs-vsoc2000.xml (limited to 'utils/regtools/desc') diff --git a/utils/regtools/desc/regs-example-v1.xml b/utils/regtools/desc/regs-example-v1.xml index 4f3cf81ff2..fcb9f7f55e 100644 --- a/utils/regtools/desc/regs-example-v1.xml +++ b/utils/regtools/desc/regs-example-v1.xml @@ -1,5 +1,5 @@ - + diff --git a/utils/regtools/desc/regs-example.xml b/utils/regtools/desc/regs-example.xml deleted file mode 100644 index 6fb8f759fe..0000000000 --- a/utils/regtools/desc/regs-example.xml +++ /dev/null @@ -1,153 +0,0 @@ - - - vsoc - Virtual SOC - Virtual SoC is a nice and powerful chip. - Amaury Pouly - ARM - 0.5 - - int - Interrupt Collector - The interrupt collector controls the routing of interrupt to the processor - - ICOLL - Interrupt collector -
0x80000000
- - - status - read-only - Interrupt status register - - STATUS -
0x4
- - - 8 - - VDDIO_BO - VDDIO brownout interrupt status - 0 - - - - - enable - Interrupt enable register - - ENABLE -
0x8
- - - 16 - - VDDIO_BO - VDDIO brownout interrupt enable - 0 - 2 - - DISABLED - Interrupt is disabled - 0 - - - ENABLED - Interrupt is enabled - 1 - - - NMI - Interrupt is non-maskable - 2 - - - - - set - 4 - - - clr - 8 - - - - - gpio - GPIO controller - A GPIO controller manages several ports - - CPU_GPIO - CPU GPIO controller 1 through 3 - - 1 - 3 - 0x80001000+(n-1)*0x1000 - - - - COP_GPIO - Companion processor GPIO controller - Although the companion processor GPIO controller is accessible from the CPU, it incurs an extra penalty on the bus -
0x90000000
- - - port - GPIO port - - PORT - - 0 - 4 - 0 - 0x100 - - - - input - Input register - - IN -
0
- - - 8 - - VALUE - 0 - 8 - - - - - output_enable - Output enable register - - OE -
0x10
- - - 8 - - ENABLE - 0 - 8 - - - - set -
4
- - - clr -
8
- - - mask -
12
- - - - - \ No newline at end of file diff --git a/utils/regtools/desc/regs-vsoc1000.xml b/utils/regtools/desc/regs-vsoc1000.xml new file mode 100644 index 0000000000..d909d85b53 --- /dev/null +++ b/utils/regtools/desc/regs-vsoc1000.xml @@ -0,0 +1,248 @@ + + + vsoc1000 + Virtual SOC 1000 + Virtual SoC 1000 is a nice chip. Its dual-core architecture makes it super powerful. + Amaury Pouly + ARM + 0.5 + + int + Interrupt Collector + The interrupt collector controls the routing of the interrupts to the processors. It has 32 interrupts sources, which can be routed as FIQ or IRQ to the main processor or the coprocessor. + + ICOLL + Interrupt collector +
0x80000000
+ + + ctrl + Control register + + CTRL +
0x0
+ + + 8 + + CLKGATE + Clock gating control + 7 + + + SFTRST + Soft reset, the bit will automatically reset to 0 when reset is completed + 6 + + + set + 4 + + + clr + 8 + + + + + status + Interrupt status register + + STATUS +
0x10
+ + + + STATUS + Bit is set to 1 is the interrupt is pending, write a 1 to the clear variant to clear it + 0 + 32 + + + clr + 8 + + + + + enable + Interrupt enable register + + ENABLE + + 0 + 32 + 0x20 + 0x10 + + + + 16 + This register controls the routing of the interrupt + + COP_PRIO + Coprocessor priority + 5 + 2 + + MASKED + Interrupt is masked + 0x0 + + + LOW + 0x1 + + + HIGH + 0x2 + + + NMI + Interrupt is non maskable + 0x3 + + + + COP_TYPE + Interrupt type + 4 + + IRQ + 0x0 + + + FIQ + 0x1 + + + + CPU_PRIO + CPU priority + 2 + 2 + + MASKED + Interrupt will never be sent to the CPU + 0x0 + + + LOW + 0x1 + + + HIGH + 0x2 + + + NMI + Interrupt is non maskable + 0x3 + + + + CPU_TYPE + Interrupt type + 1 + + IRQ + 0x0 + + + FIQ + 0x1 + + + + ENABLE + 0 + + + set + 4 + + + clr + 8 + + + + + + gpio + GPIO controller + A GPIO controller manages several ports + + CPU_GPIO + CPU GPIO controller 1 through 3 + + 1 + 3 + 0x80001000+(n-1)*0x1000 + + + + COP_GPIO + Companion processor GPIO controller + Although the companion processor GPIO controller is accessible from the CPU, it incurs an extra penalty on the bus +
0x90000000
+ + + port + GPIO port + + PORT + + 0 + 2 + 0x0 + 0x100 + + + + input + Input register + + IN +
0x0
+ + + 8 + + VALUE + 0 + 8 + + + + + output_enable + Output enable register + + OE +
0x10
+ + + 8 + + ENABLE + 0 + 8 + + + set + 4 + + + clr + 8 + + + mask + 12 + + + + + + diff --git a/utils/regtools/desc/regs-vsoc2000.xml b/utils/regtools/desc/regs-vsoc2000.xml new file mode 100644 index 0000000000..bcd6d08d38 --- /dev/null +++ b/utils/regtools/desc/regs-vsoc2000.xml @@ -0,0 +1,396 @@ + + + vsoc2000 + Virtual SOC 2000 + Virtual SoC 2000 is a nice chip. Its quad-core architecture with trustzone makes it super powerful. + Amaury Pouly + ARM + 0.5 + + int + Interrupt Collector + The interrupt collector controls the routing of the interrupts to the processors. It has 32 interrupts sources, which can be routed as FIQ or IRQ to the either processor. + + ICOLL + Interrupt collector +
0x80000000
+ + + ctrl + Control register + + CTRL +
0x0
+ + + 8 + + CLKGATE + Clock gating control. This bit can be protected by TZ lock. + 7 + + + SFTRST + Soft reset, the bit will automatically reset to 0 when reset is completed. This bit can be protected by TZ lock. + 6 + + + TZ_LOCK + Trust Zone lock + 5 + + UNLOCKED + 0x0 + + + LOCKED + When the interrupt collector is locked, only a secured processor can modify protected fields. + 0x1 + + + + set + 4 + + + clr + 8 + + + + + status + Interrupt status register + + STATUS +
0x10
+ + + + STATUS + Bit is set to 1 is the interrupt is pending, write a 1 to the clear variant to clear it. Secured interrupts can only be cleared or polled by secured processors (non-secure will always read 0 for those). + 0 + 32 + + + clr + 8 + + + + + enable + Interrupt enable register + + ENABLE + + 0 + 32 + 0x20 + 0x10 + + + + 16 + This register controls the routing of the interrupt + + CPU3_PRIO + Interrupt priority + 14 + 2 + + MASKED + Interrupt is masked + 0x0 + + + LOW + 0x1 + + + HIGH + 0x2 + + + NMI + Interrupt is non maskable + 0x3 + + + + CPU3_TYPE + Interrupt type + 13 + + IRQ + 0x0 + + + FIQ + 0x1 + + + + CPU3_TZ + Trust Zone interrupt: when set, only a secured processor can modify the parameters for secured interrupts. + 12 + + + CPU2_PRIO + 10 + 2 + + MASKED + Interrupt is masked + 0x0 + + + LOW + 0x1 + + + HIGH + 0x2 + + + NMI + Interrupt is non maskable + 0x3 + + + + CPU2_TYPE + Interrupt type + 9 + + IRQ + 0x0 + + + FIQ + 0x1 + + + + CPU2_TZ + Trust Zone interrupt: when set, only a secured processor can modify the parameters for secured interrupts. + 8 + + + CPU1_PRIO + Interrupt priority + 6 + 2 + + MASKED + Interrupt is masked + 0x0 + + + LOW + 0x1 + + + HIGH + 0x2 + + + NMI + Interrupt is non maskable + 0x3 + + + + CPU1_TYPE + Interrupt type + 5 + + IRQ + 0x0 + + + FIQ + 0x1 + + + + CPU1_TZ + Trust Zone interrupt: when set, only a secured processor can modify the parameters for secured interrupts. + 4 + + + CPU0_PRIO + Interrupt priority + 2 + 2 + + MASKED + Interrupt will never be sent to the CPU + 0x0 + + + LOW + 0x1 + + + HIGH + 0x2 + + + NMI + Interrupt is non maskable + 0x3 + + + + CPU0_TYPE + Interrupt type + 1 + + IRQ + 0x0 + + + FIQ + 0x1 + + + + CPU0_TZ + Trust Zone interrupt: when set, only a secured processor can modify the parameters for secured interrupts. + 0 + + + set + 4 + + + clr + 8 + + + + + + gpio + GPIO controller + A GPIO controller manages several ports. + + CPU_GPIO + CPU GPIO controllers 1 through 7 + + 1 + 8 + 0x80001000+(n-1)*0x1000 + + + + port + GPIO port + + PORT + + 0 + 2 + 0x0 + 0x100 + + + + input + Input register + + IN +
0x0
+ + + 8 + + VALUE + 0 + 8 + + + + + output_enable + Output enable register + + OE +
0x10
+ + + 8 + + ENABLE + 0 + 8 + + + set + 4 + + + clr + 8 + + + mask + 12 + + + + + + + tz + Trust Zone + + TZ +
0xa0000000
+ + + ctrl + Control Register + + CTRL +
0x0
+ + + 8 + + SCRATCH + TZ protected scratch value + 4 + 4 + + + DISABLE + One bit per CPU: set to 1 to prevent the processor from being able to enter TZ mode. Can only be set by a secured processor. By default all processors can enter TZ mode. + 0 + 4 + + + + + debug + Debug register + + DEBUG + Debug register + Don't touch it! + + 42 +
0x50
+
0x60
+
0x90
+
0x110
+
0x130
+ + + + 8 + + + + diff --git a/utils/regtools/desc/spec-2.0.txt b/utils/regtools/desc/spec-2.0.txt index 79b9f6be44..be97fbc41a 100644 --- a/utils/regtools/desc/spec-2.0.txt +++ b/utils/regtools/desc/spec-2.0.txt @@ -120,6 +120,23 @@ usual arithmetic operators. The example below illustrate such a use: +In the case when the addresses do not follow a regular pattern or a formula would +be too complicated, it is always possible to specify the addresses as a list: + + + N + + F + + 0 +
0x50
+
0x60
+
0x90
+
0x110
+ + + + In this example we generate four nodes F[0], ..., F[3] with a formula. Here "/" is the euclidian division and "%" is the modulo operator. Note the use of an attribute to specify which variable represents the index. The generated addresses @@ -177,6 +194,7 @@ and an optional description. The example below illustrates all these concepts: 8 + This register controls the parameters of the interrupt: priority, IRQ/FIQ and enable MODE Interrupt mode @@ -218,6 +236,10 @@ and an optional description. The example below illustrates all these concepts: 1 + + set + 0x4 + In this example, the 8-bit registers has three fields: @@ -350,7 +372,15 @@ Element: register It can contain at most one of each of the following tags: - width: width in bits (positive number) It can contain any number of the following tags: +- desc: free form description of the register - field: field description +- variant: variant description + +Element: variant +-------------- +It must contain the following tags: +- type: name of type, only made of alphanumerical characters +- offset: offset with respect to register address Element: field -------------- -- cgit v1.2.3