From 56340f4cd0a6ab318a52d2a62ded36aad2946e1d Mon Sep 17 00:00:00 2001 From: Amaury Pouly Date: Tue, 2 Aug 2016 15:18:41 +0100 Subject: hwstub: add the possibility to flush caches before exec This is needed on the jz4760b because if some data is loaded to DRAM, then it is cached and a disaster lurks if dcaches/icache are not flushed. Targets that needs this must define CONFIG_FLUSH_CACHES in target-config.h and implement target_flush_caches(). Currently MIPS has some generic code for mips32r1 that requires to define {D,I}CACHE_SIZE and {D,I}CACHE_LINE_SIZE in target-config.h Change-Id: I5a3fc085de9445d8c8a2eb61ae4e2dc9bb6b4e8e --- utils/hwstub/stub/target.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'utils/hwstub/stub/target.h') diff --git a/utils/hwstub/stub/target.h b/utils/hwstub/stub/target.h index 5cd049d04f..4992dd5bf8 100644 --- a/utils/hwstub/stub/target.h +++ b/utils/hwstub/stub/target.h @@ -41,6 +41,10 @@ uint32_t target_read32(const void *addr); void target_write8(void *addr, uint8_t val); void target_write16(void *addr, uint16_t val); void target_write32(void *addr, uint32_t val); +#ifdef CONFIG_FLUSH_CACHES +/* flush cache: commit dcache and invalidate icache */ +void target_flush_caches(void); +#endif /* mandatory for all targets */ extern struct hwstub_target_desc_t target_descriptor; -- cgit v1.2.3