From a8d1690ffec4a67fdcb0836fd91989fd1dbf5a7a Mon Sep 17 00:00:00 2001 From: Rafaël Carré Date: Thu, 25 Mar 2010 23:01:56 +0000 Subject: Make storage alignement use cache alignement macros Introduce STORAGE_ALIGN_DOWN, STORAGE_PAD (using new CACHE_PAD) and STORAGE_OVERLAP (using new CACHE_OVERLAP), make them useful only when PROC_NEEDS_CACHEALIGN and STORAGE_NEEDS_ALIGN are defined Modify PP and nano2g system-target.h accordingly git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25336 a1c6a512-1295-4272-9138-f99709370657 --- firmware/export/config.h | 17 ----------------- firmware/export/config/ipodnano2g.h | 1 - firmware/export/system.h | 18 ++++++++++++++++++ firmware/target/arm/s5l8700/system-target.h | 5 +++++ firmware/target/arm/system-target.h | 5 +++++ 5 files changed, 28 insertions(+), 18 deletions(-) (limited to 'firmware') diff --git a/firmware/export/config.h b/firmware/export/config.h index e678590b44..9d8dc41111 100644 --- a/firmware/export/config.h +++ b/firmware/export/config.h @@ -914,23 +914,6 @@ Lyre prototype 1 */ #endif /* HAVE_USBSTACK */ -/* Storage alignment: the mask specifies a mask of bits which should be - * clear in addresses used for storage_{read,write}_sectors(). This is - * only relevant for buffers that will contain one or more whole sectors. - */ - -/* PP502x DMA requires an alignment of at least 16 bytes */ -#ifdef HAVE_ATA_DMA -#ifdef CPU_PP502x -#define STORAGE_ALIGN_MASK 15 -#endif -#endif /* HAVE_ATA_DMA */ - -/* by default no alignment is required */ -#ifndef STORAGE_ALIGN_MASK -#define STORAGE_ALIGN_MASK 0 -#endif - /* This attribute can be used to enable to detection of plugin file handles leaks. * When enabled, the plugin core will monitor open/close/creat and when the plugin exits * will display an error message if the plugin leaked some file handles */ diff --git a/firmware/export/config/ipodnano2g.h b/firmware/export/config/ipodnano2g.h index 0b690416a7..989d56338d 100644 --- a/firmware/export/config/ipodnano2g.h +++ b/firmware/export/config/ipodnano2g.h @@ -219,6 +219,5 @@ //#define IPOD_ACCESSORY_PROTOCOL //#define HAVE_SERIAL -#define STORAGE_ALIGN_MASK 15 #define USB_WRITE_BUFFER_SIZE (1024*64) diff --git a/firmware/export/system.h b/firmware/export/system.h index 505b167af9..fee188802b 100644 --- a/firmware/export/system.h +++ b/firmware/export/system.h @@ -312,6 +312,16 @@ static inline void cpucache_flush(void) /* Aligns a buffer pointer and size to proper boundaries */ #define CACHEALIGN_BUFFER(start, size) \ ALIGN_BUFFER((start), (size), CACHEALIGN_SIZE) +/* Pad a size so the buffer can be aligned later */ +#define CACHE_PAD(x) ((x) + CACHEALIGN_SIZE - 1) +/* Number of bytes in the last cacheline assuming buffer of size x is aligned */ +#define CACHE_OVERLAP(x) (x & (CACHEALIGN_SIZE - 1)) + +#ifdef NEEDS_STORAGE_ALIGN +#define STORAGE_ALIGN_DOWN(x) CACHEALIGN_DOWN(x) +#define STORAGE_PAD(x) CACHE_PAD(x) +#define STORAGE_OVERLAP(x) CACHE_OVERLAP(x) +#endif #else /* ndef PROC_NEEDS_CACHEALIGN */ @@ -323,9 +333,17 @@ static inline void cpucache_flush(void) #define CACHEALIGN_DOWN(x) (x) /* Make no adjustments */ #define CACHEALIGN_BUFFER(start, size) +#define CACHE_PAD(x) (x) +#define CACHE_OVERLAP(x) 0 #endif /* PROC_NEEDS_CACHEALIGN */ +#if !defined(PROC_NEEDS_CACHEALIGN) || !defined(NEEDS_STORAGE_ALIGN) +#define STORAGE_ALIGN_DOWN(x) (x) +#define STORAGE_PAD(x) (x) +#define STORAGE_OVERLAP(x) 0 +#endif + /* Double-cast to avoid 'dereferencing type-punned pointer will * break strict aliasing rules' B.S. */ #define PUN_PTR(type, p) ((type)(intptr_t)(p)) diff --git a/firmware/target/arm/s5l8700/system-target.h b/firmware/target/arm/s5l8700/system-target.h index 81e5c7f7fd..c531344b64 100644 --- a/firmware/target/arm/s5l8700/system-target.h +++ b/firmware/target/arm/s5l8700/system-target.h @@ -29,6 +29,11 @@ #define CPUFREQ_NORMAL 47923200 #define CPUFREQ_MAX 191692800 +/* DMA engine needs aligned addresses */ +#define PROC_NEEDS_CACHEALIGN +#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ +#define NEEDS_STORAGE_ALIGN + #define inl(a) (*(volatile unsigned long *) (a)) #define outl(a,b) (*(volatile unsigned long *) (b) = (a)) #define inb(a) (*(volatile unsigned char *) (a)) diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h index 764cd18d15..1422e6467a 100644 --- a/firmware/target/arm/system-target.h +++ b/firmware/target/arm/system-target.h @@ -22,6 +22,7 @@ #ifndef SYSTEM_TARGET_H #define SYSTEM_TARGET_H +#include "config.h" #include "system-arm.h" #ifdef CPU_PP @@ -162,6 +163,10 @@ static inline void wake_core(int core) #define PROC_NEEDS_CACHEALIGN #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ +#if defined(CPU_PP502x) && defined(HAVE_ATA_DMA) +#define NEEDS_STORAGE_ALIGN +#endif + /** cache functions **/ #ifndef BOOTLOADER #define HAVE_CPUCACHE_INVALIDATE -- cgit v1.2.3