From 8de163b8ae139931ddd2daabe8af0bd5fffc67f1 Mon Sep 17 00:00:00 2001 From: Tomasz Moń Date: Fri, 9 Jul 2021 14:16:05 +0200 Subject: Sansa Connect: Fix reported CPU frequency Make frequency related comments accurate. Disable UART0 clock. Change-Id: I224a3d6656ad53165dcff68ed716fa2c6863240d --- .../tms320dm320/sansa-connect/avr-sansaconnect.c | 5 +- .../arm/tms320dm320/sansa-connect/crt0-board.S | 64 ++++++++++++++-------- .../tms320dm320/sansa-connect/lcd-sansaconnect.c | 2 +- .../tms320dm320/sansa-connect/wifi-sansaconnect.c | 4 +- firmware/target/arm/tms320dm320/sdmmc-dm320.c | 5 +- firmware/target/arm/tms320dm320/system-dm320.c | 9 ++- firmware/target/arm/tms320dm320/system-target.h | 7 ++- 7 files changed, 66 insertions(+), 30 deletions(-) (limited to 'firmware') diff --git a/firmware/target/arm/tms320dm320/sansa-connect/avr-sansaconnect.c b/firmware/target/arm/tms320dm320/sansa-connect/avr-sansaconnect.c index 01acc6905e..6fd504a0f8 100644 --- a/firmware/target/arm/tms320dm320/sansa-connect/avr-sansaconnect.c +++ b/firmware/target/arm/tms320dm320/sansa-connect/avr-sansaconnect.c @@ -501,7 +501,10 @@ void avr_hid_init(void) bitclr16(&IO_GIO_DIR2, (1 << 0)); avr_hid_release(); - /* RATE = 219 (0xDB) -> 200 kHz */ + /* Master, MSB first, RATE = 219 (Bit rate = ARM clock / 2*(RATE + 1))) + * Boosted 148.5 MHz / 440 = 337.5 kHz + * Default 74.25 MHz / 440 = 168.75 kHz + */ IO_SERIAL1_MODE = 0x6DB; mutex_init(&avr_mtx); diff --git a/firmware/target/arm/tms320dm320/sansa-connect/crt0-board.S b/firmware/target/arm/tms320dm320/sansa-connect/crt0-board.S index a356016fb4..1848143fc1 100644 --- a/firmware/target/arm/tms320dm320/sansa-connect/crt0-board.S +++ b/firmware/target/arm/tms320dm320/sansa-connect/crt0-board.S @@ -58,10 +58,10 @@ _init_board: /* Setup the EMIF interface timings */ /* FLASH interface: - * These are based on the OF setup + * These are based on the OF setup */ /* IO_EMIF_CS0CTRL1 and - * IO_EMIF_CS0CTRL2 + * IO_EMIF_CS0CTRL2 */ mwh 0x30A00, 0x889A mwh 0x30A02, 0x1110 @@ -75,7 +75,7 @@ _init_board: mwh 0x30A0E, 0x0222 /* IO_EMIF_CS3CTRL1 and - * IO_EMIF_CS3CTRL2 + * IO_EMIF_CS3CTRL2 */ mwh 0x30A10, 0x8899 mwh 0x30A12, 0x5110 @@ -96,37 +96,49 @@ _init_board: _clock_setup: /* Clock initialization */ + /* Disable peripheral clocks */ + mwhm 0x3089A, 0 + mwhm 0x3089C, 0 + /* IO_CLK_BYP: Bypass the PLLs for the following changes */ mwh 0x30894, 0x1111 /* - * IO_CLK_PLLA - * IO_CLK_PLLB + * IO_CLK_PLLA: 27 MHz * 11 / 1 = 297 MHz + * IO_CLK_PLLB: 27 MHz */ - mwhm 0x30880, 0x00A0 + mwh 0x30880, 0x10A0 mwhm 0x30882, 0x1000 - /* IO_CLK_SEL0 */ + /* IO_CLK_SEL0: Timer 0 and 1, UART 0 and 1 from PLLIN (27 MHz) */ mwh 0x30884, 0x0066 - /* IO_CLK_SEL1 */ + /* IO_CLK_SEL1: VENC from PLLA, OSD clock = VENC clock / 2 */ mwhm 0x30886, 0x0003 - # IO_CLK_SEL2: ARM, AXL, SDRAM and DSP are from PLLA */ + /* IO_CLK_SEL2: ARM, AXL, SDRAM and DSP are from PLLA */ mwh 0x30888, 0 - /* IO_CLK_DIV0: Set the slow clock speed for the ARM/AHB */ + /* IO_CLK_DIV0: Set the fast clock speed for the ARM/AHB + * ARM = PLLA / 2 = 148.5 MHz + * AHB = ARM / 2 = 74.25 MHz + */ mwh 0x3088A, 0x0101 - /* IO_CLK_DIV1: Accelerator, SDRAM */ + /* IO_CLK_DIV1: Accelerator, SDRAM + * AXL = PLLA / 2 = 148.5 MHz + * SDRAM = PLLA / 3 = 99 MHz + */ mwh 0x3088C, 0x0102 /* IO_CLK_DIV2: DSP, MS Clock * OF must be booted with this value + * DSP = PLLA / 3 = 99 MHz + * MS = PLLA / 1 = 297 MHz */ mwhm 0x3088E, 0x0200 - # PLLA &= ~0x1000 (BIC #0x1000) + /* PLLA &= ~0x1000 (BIC #0x1000) */ mrh 0x30880 bic r0, r0, #0x1000 strh r0, [r1] @@ -141,25 +153,27 @@ _plla_wait: /* IO_CLK_BYP: Enable PLL feeds */ mwhm 0x30894, 0x0 - /* IO_CLK_MOD0 */ + /* IO_CLK_MOD0 + * Enable clocks: + * ARM, Bus Controller, AHB, ARM internal memory, EMIF, SDRAM + * Disable clocks: + * ETM, E2ICE, INTC, EXTHOST, DSP, HPIB + */ mwh 0x30898, 0x01A7 - /* IO_CLK_MOD1 */ - mwhm 0x3089A, 0x18 - - /* IO_CLK_MOD2 */ - mwhm 0x3089C, 0x4A0 + /* IO_CLK_MOD2: Enable GIO and SIF1 clocks */ + mwhm 0x3089C, 0x0420 /* Setup the SDRAM range on the AHB bus */ /* SDRAMSA */ mov r0, #0x60000 mov r1, #0x1000000 str r1, [r0, #0xF00] - + /* SDRAMEA: 64MB */ mov r1, #0x5000000 str r1, [r0, #0xF04] - + /* SDRC_REFCTL */ mwh 0x309A8, 0 @@ -183,8 +197,11 @@ _plla_wait: mwhm 0x309A8, 0x0140 + /* IMGBUF SDRAM priority bit 2 set */ mwhm 0x309BE, 0x4 + /* SDRAM refresh priority bit 1 set */ mwhm 0x309BC, 0x2 + /* Use defined priority bits */ ldr r0, =0x309C4 ldr r1, [r0] orr r1, r1, #1 @@ -198,10 +215,11 @@ _plla_wait: orr r1, r1, #0x40 strh r1, [r0] + /* Enable auto refresh with interval (64 + 1) * 8 SDRAM clocks */ mwhm 0x309A8, 0x0140 /* Go through the GPIO initialization */ - /* Warning: setting some of the functions wrong will make OF unable + /* Warning: setting some of the functions wrong will make OF unable to boot (freeze during startup) */ /* IO_GIO_FSEL0: Set up the GPIO pin functions 0-16 */ mwhm 0x305A4, 0xC000 @@ -223,7 +241,7 @@ _plla_wait: /* IO_GIO_DIR2 */ mwh 0x30584, 0x01FD - + /* IO_GIO_INV0 */ mwh 0x30586, 0x0000 @@ -235,6 +253,6 @@ _plla_wait: bx lr -.ltorg +.ltorg .size _init_board, .-_init_board diff --git a/firmware/target/arm/tms320dm320/sansa-connect/lcd-sansaconnect.c b/firmware/target/arm/tms320dm320/sansa-connect/lcd-sansaconnect.c index 9d58fccdb3..1143dd2ca8 100644 --- a/firmware/target/arm/tms320dm320/sansa-connect/lcd-sansaconnect.c +++ b/firmware/target/arm/tms320dm320/sansa-connect/lcd-sansaconnect.c @@ -141,7 +141,7 @@ void lcd_init_device(void) VENC Clock from PLLA */ IO_CLK_SEL1 = 0x3; - /* Set VENC Clock Division to 11 + /* Set VENC Clock Division to 11 (PLLA / 11 = 297 MHz / 11 = 27 MHz) OF bootloader sets division to 8, vmlinux sets it to 11 */ IO_CLK_DIV3 = (IO_CLK_DIV3 & ~(0x1F00)) | 0xB00; diff --git a/firmware/target/arm/tms320dm320/sansa-connect/wifi-sansaconnect.c b/firmware/target/arm/tms320dm320/sansa-connect/wifi-sansaconnect.c index 867b1da477..1f201ca1c9 100644 --- a/firmware/target/arm/tms320dm320/sansa-connect/wifi-sansaconnect.c +++ b/firmware/target/arm/tms320dm320/sansa-connect/wifi-sansaconnect.c @@ -40,7 +40,9 @@ void libertas_spi_init(void) IO_SERIAL0_TX_ENABLE = 0x0001; /* SELSDEN = 0, SLVEN = 0, SIOCLR = 0, SCLKM = 1, MSB = 1, MSSEL = 0, - * RATE = 2 -> 15MHz + * RATE = 1 (Bit rate = ARM clock / 2*(RATE + 1))) + * Boosted 148.5 MHz / 4 = 37.125 MHz + * Default 74.25 MHz / 4 = 18.5625 MHz */ IO_SERIAL0_MODE = 0x0601; diff --git a/firmware/target/arm/tms320dm320/sdmmc-dm320.c b/firmware/target/arm/tms320dm320/sdmmc-dm320.c index 33354a3146..e66a4cb3c7 100644 --- a/firmware/target/arm/tms320dm320/sdmmc-dm320.c +++ b/firmware/target/arm/tms320dm320/sdmmc-dm320.c @@ -805,8 +805,9 @@ int sd_init(void) bitclr16(&IO_CLK_MOD2, CLK_MOD2_MMC); bitset16(&IO_CLK_INV, CLK_INV_MMC); - /* mmc module clock: 75 Mhz (AHB) / 2 = ~37.5 Mhz - * (Frequencies above are taken from Sansa Connect's OF source code) */ + /* mmc module clock when boosted 74.25 Mhz (AHB) / 2 = 37.125 Mhz + * default 37.125 (AHB) / 2 = 18.5625 MHz + * (Frequencies above are valid for Sansa Connect) */ IO_CLK_DIV3 = (IO_CLK_DIV3 & 0xFF00) | 0x01; bitset16(&IO_CLK_MOD2, CLK_MOD2_MMC); diff --git a/firmware/target/arm/tms320dm320/system-dm320.c b/firmware/target/arm/tms320dm320/system-dm320.c index c80082afd8..6cf616184d 100644 --- a/firmware/target/arm/tms320dm320/system-dm320.c +++ b/firmware/target/arm/tms320dm320/system-dm320.c @@ -312,7 +312,14 @@ void system_init(void) #endif { #ifdef SANSA_CONNECT - /* Setting AHB divisor to 0 increases power consumption */ + /* Setting AHB divisor to 0 increases power consumption + * Slow Setup: + * ARM div = 4 ( 74.25 MHz ) + * AHB div = 2 ( 37.125 MHz ) + * Fast Setup: + * ARM div = 2 ( 148.5 MHz ) + * AHB div = 2 ( 74.25 MHz ) + */ clock_arm_slow = (1 << 8) | 3; clock_arm_fast = (1 << 8) | 1; #else diff --git a/firmware/target/arm/tms320dm320/system-target.h b/firmware/target/arm/tms320dm320/system-target.h index 1c46e909ed..9aa8b3e213 100644 --- a/firmware/target/arm/tms320dm320/system-target.h +++ b/firmware/target/arm/tms320dm320/system-target.h @@ -24,10 +24,15 @@ #include "system-arm.h" #include "mmu-arm.h" -#define CPUFREQ_SLEEP 32768 +#ifdef SANSA_CONNECT +#define CPUFREQ_DEFAULT 74250000 +#define CPUFREQ_NORMAL 74250000 +#define CPUFREQ_MAX 148500000 +#else #define CPUFREQ_DEFAULT 87500000 #define CPUFREQ_NORMAL 87500000 #define CPUFREQ_MAX 175000000 +#endif void udelay(int usec); void mdelay(int msec); -- cgit v1.2.3