From 7c6194078ca607bd5f364e139ba871b3e4ec0204 Mon Sep 17 00:00:00 2001 From: Boris Gjenero Date: Mon, 6 Apr 2009 02:46:42 +0000 Subject: FS#10086 - Playback and recording sample rate setting on the 5G iPod git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20635 a1c6a512-1295-4272-9138-f99709370657 --- firmware/drivers/audio/wm8758.c | 49 ++++++++++++++++++++++++++++++-------- firmware/export/config-ipodvideo.h | 6 +++-- firmware/export/wm8758.h | 1 + 3 files changed, 44 insertions(+), 12 deletions(-) (limited to 'firmware') diff --git a/firmware/drivers/audio/wm8758.c b/firmware/drivers/audio/wm8758.c index b8bf0906e3..bb05960ced 100644 --- a/firmware/drivers/audio/wm8758.c +++ b/firmware/drivers/audio/wm8758.c @@ -172,20 +172,49 @@ void audiohw_close(void) /* Note: Disable output before calling this function */ void audiohw_set_frequency(int fsel) { - /**** We force 44.1KHz for now. ****/ - (void)fsel; + /* CLKCTRL_MCLKDIV_MASK and ADDCTRL_SR_MASK don't overlap, + so they can both fit in one byte. Bit 0 selects PLL + configuration via pll_setups. + */ + static const unsigned char freq_setups[HW_NUM_FREQ] = + { + [HW_FREQ_48] = CLKCTRL_MCLKDIV_2 | ADDCTRL_SR_48kHz | 1, + [HW_FREQ_44] = CLKCTRL_MCLKDIV_2 | ADDCTRL_SR_48kHz, + [HW_FREQ_32] = CLKCTRL_MCLKDIV_3 | ADDCTRL_SR_32kHz | 1, + [HW_FREQ_24] = CLKCTRL_MCLKDIV_4 | ADDCTRL_SR_24kHz | 1, + [HW_FREQ_22] = CLKCTRL_MCLKDIV_4 | ADDCTRL_SR_24kHz, + [HW_FREQ_16] = CLKCTRL_MCLKDIV_6 | ADDCTRL_SR_16kHz | 1, + [HW_FREQ_12] = CLKCTRL_MCLKDIV_8 | ADDCTRL_SR_12kHz | 1, + [HW_FREQ_11] = CLKCTRL_MCLKDIV_8 | ADDCTRL_SR_12kHz, + [HW_FREQ_8] = CLKCTRL_MCLKDIV_12 | ADDCTRL_SR_8kHz | 1 + }; + + /* Each PLL configuration is an array consisting of + { PLLN, PLLK1, PLLK2, PLLK3 }. The WM8983 datasheet requires + 5 < PLLN < 13, and states optimum is PLLN = 8, f2 = 90 MHz + */ + static const unsigned short pll_setups[2][4] = + { + /* f1 = 12 MHz, R = 7.5264, f2 = 90.3168 MHz, fPLLOUT = 22.5792 MHz */ + { PLLN_PLLPRESCALE | 0x7, 0x21, 0x161, 0x26 }, + /* f1 = 12 MHz, R = 8.192, f2 = 98.304 MHz, fPLLOUT = 24.576 MHz */ + { PLLN_PLLPRESCALE | 0x8, 0xC, 0x93, 0xE9 } + }; + + int i; - /* setup PLL for MHZ=11.2896 */ - wmcodec_write(PLLN, PLLN_PLLPRESCALE | 0x7); - wmcodec_write(PLLK1, 0x21); - wmcodec_write(PLLK2, 0x161); - wmcodec_write(PLLK3, 0x26); + /* PLLN, PLLK1, PLLK2, PLLK3 are contiguous (at 0x24 to 0x27) */ + for (i = 0; i < 4; i++) + wmcodec_write(PLLN + i, pll_setups[freq_setups[fsel] & 1][i]); - /* set clock div */ - wmcodec_write(CLKCTRL, CLKCTRL_CLKSEL | CLKCTRL_MCLKDIV_2 + /* CLKCTRL_MCLKDIV divides fPLLOUT to get SYSCLK (256 * sample rate) */ + wmcodec_write(CLKCTRL, CLKCTRL_CLKSEL + | (freq_setups[fsel] & CLKCTRL_MCLKDIV_MASK) | CLKCTRL_BCLKDIV_2 | CLKCTRL_MS); - wmcodec_write(ADDCTRL, ADDCTRL_SR_48kHz | ADDCTRL_SLOWCLKEN); + /* set ADC and DAC filter characteristics according to sample rate */ + wmcodec_write(ADDCTRL, (freq_setups[fsel] & ADDCTRL_SR_MASK) + | ADDCTRL_SLOWCLKEN); /* SLOWCLK enabled for zero cross timeout to work */ } diff --git a/firmware/export/config-ipodvideo.h b/firmware/export/config-ipodvideo.h index 0ad3b5c7f2..c9f97dcea5 100644 --- a/firmware/export/config-ipodvideo.h +++ b/firmware/export/config-ipodvideo.h @@ -21,10 +21,12 @@ #define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_LINEIN) /* define the bitmask of hardware sample rates */ -#define HW_SAMPR_CAPS (SAMPR_CAP_44) +#define HW_SAMPR_CAPS (SAMPR_CAP_48 | SAMPR_CAP_44 | SAMPR_CAP_32 | \ + SAMPR_CAP_24 | SAMPR_CAP_22 | SAMPR_CAP_16 | \ + SAMPR_CAP_12 | SAMPR_CAP_11 | SAMPR_CAP_8) /* define the bitmask of recording sample rates */ -#define REC_SAMPR_CAPS (SAMPR_CAP_44) +#define REC_SAMPR_CAPS HW_SAMPR_CAPS /* define this if you have a bitmap LCD display */ #define HAVE_LCD_BITMAP diff --git a/firmware/export/wm8758.h b/firmware/export/wm8758.h index 2c7c9e109d..29304b8794 100644 --- a/firmware/export/wm8758.h +++ b/firmware/export/wm8758.h @@ -107,6 +107,7 @@ extern void audiohw_set_mixer_vol(int channel1, int channel2); #define CLKCTRL_MCLKDIV_6 (5 << 5) #define CLKCTRL_MCLKDIV_8 (6 << 5) #define CLKCTRL_MCLKDIV_12 (7 << 5) +#define CLKCTRL_MCLKDIV_MASK (7 << 5) #define CLKCTRL_CLKSEL (1 << 8) #define ADDCTRL 0x07 -- cgit v1.2.3