From b632ddf9caf27cc055c584f6e61d537fc6820b7e Mon Sep 17 00:00:00 2001 From: Maurus Cuelenaere Date: Mon, 14 Jul 2008 15:19:29 +0000 Subject: And set svn:eol-style ... git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18034 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/mips/ingenic_jz47xx/crt0.S | 492 ++++++++++----------- .../ingenic_jz47xx/onda_vx747/button-onda_vx747.c | 246 +++++------ 2 files changed, 369 insertions(+), 369 deletions(-) (limited to 'firmware/target') diff --git a/firmware/target/mips/ingenic_jz47xx/crt0.S b/firmware/target/mips/ingenic_jz47xx/crt0.S index 6ac9ad71ab..43daa2d720 100644 --- a/firmware/target/mips/ingenic_jz47xx/crt0.S +++ b/firmware/target/mips/ingenic_jz47xx/crt0.S @@ -1,246 +1,246 @@ -/* - * init.S - * - * Initialization code for JzRISC. - * - * Author: Seeger Chin - * e-mail: seeger.chin@gmail.com - * - * Copyright (C) 2006 Ingenic Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include "config.h" -#include "mips.h" - - .text - - .set mips3 - - .extern main - - .global _start -#ifdef BOOTLOADER - .section .init.text,"ax",%progbits -#else - .section .resetvectors,"ax",%progbits -#endif - .set noreorder - .set noat - -#ifdef BOOTLOADER - .word 0 /* HACK */ - .word 0 /* HACK */ -#endif -_start: - la ra, _start - //---------------------------------------------------- - // init cp0 registers. - //---------------------------------------------------- - mtc0 zero, C0_WATCHLO - mtc0 zero, C0_WATCHHI - - li t0, (M_StatusBEV | M_StatusIM7 | M_StatusIM6 \ - | M_StatusIM5 | M_StatusIM4 | M_StatusIM3 \ - | M_StatusIM2 | M_StatusERL) - // BEV = Enable Boot Exception Vectors - // IMx = Interrupt mask - // ERL = Denotes error level - mtc0 t0, C0_STATUS - - li t1, M_CauseIV - mtc0 t1, C0_CAUSE - - //---------------------------------------------------- - // init caches, assumes a 4way*128set*32byte i/d cache - //---------------------------------------------------- - li t0, 3 // enable cache for kseg0 accesses - mtc0 t0, C0_CONFIG // CONFIG reg - la t0, 0x80000000 // an idx op should use a unmappable address - ori t1, t0, 0x4000 // 16kB cache - mtc0 zero, C0_TAGLO // TAGLO reg - mtc0 zero, C0_TAGHI // TAGHI reg - -_init_cache_loop: - cache 0x8, 0(t0) // index store icache tag - cache 0x9, 0(t0) // index store dcache tag - bne t0, t1, _init_cache_loop - addiu t0, t0, 0x20 // 32 bytes per cache line - nop - - //---------------------------------------------------- - // Invalidate BTB - //---------------------------------------------------- - mfc0 t0, C0_CONFIG - nop - ori t0, 2 - mtc0 t0, C0_CONFIG - nop - - //---------------------------------------------------- - // setup stack, jump to C code - //---------------------------------------------------- - la sp, stackend - la t0, stackbegin - li t1, 0xDEADBEEF - -_init_stack_loop: - sw t1, 0(t0) - bne t0, sp, _init_stack_loop - addiu t0, t0, 4 - - la t0, main - jr t0 - nop - - -#ifndef BOOTLOADER - .section .vectors,"ax",%progbits -#endif - .extern exception_handler - .global except_common_entry - .type except_common_entry,@function -except_common_entry: - la k0, exception_handler - jr k0 - nop - nop - nop - - .extern _int - .extern _exception - .global exception_handler - .type exception_handler,@function - .set noreorder -exception_handler: - - - addiu sp, -0x80 # Add Immediate Unsigned - sw ra, 0(sp) # Store Word - sw fp, 4(sp) # Store Word - sw gp, 8(sp) # Store Word - sw t9, 0xC(sp) # Store Word - sw t8, 0x10(sp) # Store Word - sw s7, 0x14(sp) # Store Word - sw s6, 0x18(sp) # Store Word - sw s5, 0x1C(sp) # Store Word - sw s4, 0x20(sp) # Store Word - sw s3, 0x24(sp) # Store Word - sw s2, 0x28(sp) # Store Word - sw s1, 0x2C(sp) # Store Word - sw s0, 0x30(sp) # Store Word - sw t7, 0x34(sp) # Store Word - sw t6, 0x38(sp) # Store Word - sw t5, 0x3C(sp) # Store Word - sw t4, 0x40(sp) # Store Word - sw t3, 0x44(sp) # Store Word - sw t2, 0x48(sp) # Store Word - sw t1, 0x4C(sp) # Store Word - sw t0, 0x50(sp) # Store Word - sw a3, 0x54(sp) # Store Word - sw a2, 0x58(sp) # Store Word - sw a1, 0x5C(sp) # Store Word - sw a0, 0x60(sp) # Store Word - sw v1, 0x64(sp) # Store Word - sw v0, 0x68(sp) # Store Word - sw $1, 0x6C(sp) # Store Word - mflo t0 # Move F LO - nop - sw t0, 0x70(sp) # Store Word - mfhi t0 # Move F HI - nop - sw t0, 0x74(sp) # Store Word - mfc0 t0, C0_STATUS # Status register - sll zero, 1 # Shift Left Logical - sll zero, 1 # Shift Left Logical - sll zero, 1 # Shift Left Logical - sll zero, 1 # Shift Left Logical - sw t0, 0x78(sp) # Store Word - mfc0 t0, C0_EPC # Exception Program Counter - sll zero, 1 # Shift Left Logical - sll zero, 1 # Shift Left Logical - sll zero, 1 # Shift Left Logical - sll zero, 1 # Shift Left Logical - sw t0, 0x7C(sp) # Store Word - li k1, 0x7C # Load Immediate - mfc0 k0, C0_CAUSE # C0_CAUSE of last exception - and k0, k1 # AND - beq zero, k0, _int # Branch on Equal - nop - la k0, _exception - jr k0 - nop - - .global _int - .type _int,@function -_int: - jal intr_handler # Jump And Link - nop - lw ra, 0(sp) # Load Word - lw fp, 4(sp) # Load Word - sw gp, 8(sp) # Store Word - lw t9, 0xC(sp) # Load Word - lw t8, 0x10(sp) # Load Word - lw s7, 0x14(sp) # Load Word - lw s6, 0x18(sp) # Load Word - lw s5, 0x1C(sp) # Load Word - lw s4, 0x20(sp) # Load Word - lw s3, 0x24(sp) # Load Word - lw s2, 0x28(sp) # Load Word - lw s1, 0x2C(sp) # Load Word - lw s0, 0x30(sp) # Load Word - lw t7, 0x34(sp) # Load Word - lw t6, 0x38(sp) # Load Word - lw t5, 0x3C(sp) # Load Word - lw t4, 0x40(sp) # Load Word - lw t3, 0x44(sp) # Load Word - lw t2, 0x48(sp) # Load Word - lw t1, 0x4C(sp) # Load Word - lw t0, 0x50(sp) # Load Word - lw a3, 0x54(sp) # Load Word - lw a2, 0x58(sp) # Load Word - lw a1, 0x5C(sp) # Load Word - lw a0, 0x60(sp) # Load Word - lw v1, 0x64(sp) # Load Word - lw v0, 0x68(sp) # Load Word - lw v1, 0x6C(sp) # Load Word - lw k0, 0x70(sp) # Load Word - mtlo k0 # Move To LO - nop - lw k0, 0x74(sp) # Load Word - mthi k0 # Move To HI - nop - lw k0, 0x78(sp) # Load Word - nop - mtc0 k0, C0_STATUS # Status register - sll zero, 1 # Shift Left Logical - sll zero, 1 # Shift Left Logical - sll zero, 1 # Shift Left Logical - sll zero, 1 # Shift Left Logical - lw k0, 0x7C(sp) # Load Word - nop - mtc0 k0, C0_EPC # Exception Program Counter - sll zero, 1 # Shift Left Logical - sll zero, 1 # Shift Left Logical - sll zero, 1 # Shift Left Logical - sll zero, 1 # Shift Left Logical - addiu sp, 0x80 # Add Immediate Unsigned - eret # Exception Return - nop - - .extern _except_handler - .global _exception - .type _exception,@function -_exception: - move a0, sp - mfc0 a1, C0_CAUSE # C0_CAUSE of last exception - mfc0 a2, C0_EPC # Exception Program Counter - la k0, except_handler # Load Address - jr k0 # Jump Register - nop - - .set reorder +/* + * init.S + * + * Initialization code for JzRISC. + * + * Author: Seeger Chin + * e-mail: seeger.chin@gmail.com + * + * Copyright (C) 2006 Ingenic Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include "config.h" +#include "mips.h" + + .text + + .set mips3 + + .extern main + + .global _start +#ifdef BOOTLOADER + .section .init.text,"ax",%progbits +#else + .section .resetvectors,"ax",%progbits +#endif + .set noreorder + .set noat + +#ifdef BOOTLOADER + .word 0 /* HACK */ + .word 0 /* HACK */ +#endif +_start: + la ra, _start + //---------------------------------------------------- + // init cp0 registers. + //---------------------------------------------------- + mtc0 zero, C0_WATCHLO + mtc0 zero, C0_WATCHHI + + li t0, (M_StatusBEV | M_StatusIM7 | M_StatusIM6 \ + | M_StatusIM5 | M_StatusIM4 | M_StatusIM3 \ + | M_StatusIM2 | M_StatusERL) + // BEV = Enable Boot Exception Vectors + // IMx = Interrupt mask + // ERL = Denotes error level + mtc0 t0, C0_STATUS + + li t1, M_CauseIV + mtc0 t1, C0_CAUSE + + //---------------------------------------------------- + // init caches, assumes a 4way*128set*32byte i/d cache + //---------------------------------------------------- + li t0, 3 // enable cache for kseg0 accesses + mtc0 t0, C0_CONFIG // CONFIG reg + la t0, 0x80000000 // an idx op should use a unmappable address + ori t1, t0, 0x4000 // 16kB cache + mtc0 zero, C0_TAGLO // TAGLO reg + mtc0 zero, C0_TAGHI // TAGHI reg + +_init_cache_loop: + cache 0x8, 0(t0) // index store icache tag + cache 0x9, 0(t0) // index store dcache tag + bne t0, t1, _init_cache_loop + addiu t0, t0, 0x20 // 32 bytes per cache line + nop + + //---------------------------------------------------- + // Invalidate BTB + //---------------------------------------------------- + mfc0 t0, C0_CONFIG + nop + ori t0, 2 + mtc0 t0, C0_CONFIG + nop + + //---------------------------------------------------- + // setup stack, jump to C code + //---------------------------------------------------- + la sp, stackend + la t0, stackbegin + li t1, 0xDEADBEEF + +_init_stack_loop: + sw t1, 0(t0) + bne t0, sp, _init_stack_loop + addiu t0, t0, 4 + + la t0, main + jr t0 + nop + + +#ifndef BOOTLOADER + .section .vectors,"ax",%progbits +#endif + .extern exception_handler + .global except_common_entry + .type except_common_entry,@function +except_common_entry: + la k0, exception_handler + jr k0 + nop + nop + nop + + .extern _int + .extern _exception + .global exception_handler + .type exception_handler,@function + .set noreorder +exception_handler: + + + addiu sp, -0x80 # Add Immediate Unsigned + sw ra, 0(sp) # Store Word + sw fp, 4(sp) # Store Word + sw gp, 8(sp) # Store Word + sw t9, 0xC(sp) # Store Word + sw t8, 0x10(sp) # Store Word + sw s7, 0x14(sp) # Store Word + sw s6, 0x18(sp) # Store Word + sw s5, 0x1C(sp) # Store Word + sw s4, 0x20(sp) # Store Word + sw s3, 0x24(sp) # Store Word + sw s2, 0x28(sp) # Store Word + sw s1, 0x2C(sp) # Store Word + sw s0, 0x30(sp) # Store Word + sw t7, 0x34(sp) # Store Word + sw t6, 0x38(sp) # Store Word + sw t5, 0x3C(sp) # Store Word + sw t4, 0x40(sp) # Store Word + sw t3, 0x44(sp) # Store Word + sw t2, 0x48(sp) # Store Word + sw t1, 0x4C(sp) # Store Word + sw t0, 0x50(sp) # Store Word + sw a3, 0x54(sp) # Store Word + sw a2, 0x58(sp) # Store Word + sw a1, 0x5C(sp) # Store Word + sw a0, 0x60(sp) # Store Word + sw v1, 0x64(sp) # Store Word + sw v0, 0x68(sp) # Store Word + sw $1, 0x6C(sp) # Store Word + mflo t0 # Move F LO + nop + sw t0, 0x70(sp) # Store Word + mfhi t0 # Move F HI + nop + sw t0, 0x74(sp) # Store Word + mfc0 t0, C0_STATUS # Status register + sll zero, 1 # Shift Left Logical + sll zero, 1 # Shift Left Logical + sll zero, 1 # Shift Left Logical + sll zero, 1 # Shift Left Logical + sw t0, 0x78(sp) # Store Word + mfc0 t0, C0_EPC # Exception Program Counter + sll zero, 1 # Shift Left Logical + sll zero, 1 # Shift Left Logical + sll zero, 1 # Shift Left Logical + sll zero, 1 # Shift Left Logical + sw t0, 0x7C(sp) # Store Word + li k1, 0x7C # Load Immediate + mfc0 k0, C0_CAUSE # C0_CAUSE of last exception + and k0, k1 # AND + beq zero, k0, _int # Branch on Equal + nop + la k0, _exception + jr k0 + nop + + .global _int + .type _int,@function +_int: + jal intr_handler # Jump And Link + nop + lw ra, 0(sp) # Load Word + lw fp, 4(sp) # Load Word + sw gp, 8(sp) # Store Word + lw t9, 0xC(sp) # Load Word + lw t8, 0x10(sp) # Load Word + lw s7, 0x14(sp) # Load Word + lw s6, 0x18(sp) # Load Word + lw s5, 0x1C(sp) # Load Word + lw s4, 0x20(sp) # Load Word + lw s3, 0x24(sp) # Load Word + lw s2, 0x28(sp) # Load Word + lw s1, 0x2C(sp) # Load Word + lw s0, 0x30(sp) # Load Word + lw t7, 0x34(sp) # Load Word + lw t6, 0x38(sp) # Load Word + lw t5, 0x3C(sp) # Load Word + lw t4, 0x40(sp) # Load Word + lw t3, 0x44(sp) # Load Word + lw t2, 0x48(sp) # Load Word + lw t1, 0x4C(sp) # Load Word + lw t0, 0x50(sp) # Load Word + lw a3, 0x54(sp) # Load Word + lw a2, 0x58(sp) # Load Word + lw a1, 0x5C(sp) # Load Word + lw a0, 0x60(sp) # Load Word + lw v1, 0x64(sp) # Load Word + lw v0, 0x68(sp) # Load Word + lw v1, 0x6C(sp) # Load Word + lw k0, 0x70(sp) # Load Word + mtlo k0 # Move To LO + nop + lw k0, 0x74(sp) # Load Word + mthi k0 # Move To HI + nop + lw k0, 0x78(sp) # Load Word + nop + mtc0 k0, C0_STATUS # Status register + sll zero, 1 # Shift Left Logical + sll zero, 1 # Shift Left Logical + sll zero, 1 # Shift Left Logical + sll zero, 1 # Shift Left Logical + lw k0, 0x7C(sp) # Load Word + nop + mtc0 k0, C0_EPC # Exception Program Counter + sll zero, 1 # Shift Left Logical + sll zero, 1 # Shift Left Logical + sll zero, 1 # Shift Left Logical + sll zero, 1 # Shift Left Logical + addiu sp, 0x80 # Add Immediate Unsigned + eret # Exception Return + nop + + .extern _except_handler + .global _exception + .type _exception,@function +_exception: + move a0, sp + mfc0 a1, C0_CAUSE # C0_CAUSE of last exception + mfc0 a2, C0_EPC # Exception Program Counter + la k0, except_handler # Load Address + jr k0 # Jump Register + nop + + .set reorder diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx747/button-onda_vx747.c b/firmware/target/mips/ingenic_jz47xx/onda_vx747/button-onda_vx747.c index e42325bcb3..90dc0b83fb 100644 --- a/firmware/target/mips/ingenic_jz47xx/onda_vx747/button-onda_vx747.c +++ b/firmware/target/mips/ingenic_jz47xx/onda_vx747/button-onda_vx747.c @@ -1,123 +1,123 @@ -/*************************************************************************** - * __________ __ ___. - * Open \______ \ ____ ____ | | _\_ |__ _______ ___ - * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / - * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < - * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ - * \/ \/ \/ \/ \/ - * $Id$ - * - * Copyright (C) 2008 by Maurus Cuelenaere - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY - * KIND, either express or implied. - * - ****************************************************************************/ - -#include "config.h" -#include "jz4740.h" -#include "button-target.h" - -#define BTN_VOL_DOWN (1 << 27) -#define BTN_VOL_UP (1 << 0) -#define BTN_MENU (1 << 1) -#define BTN_OFF (1 << 29) -#define BTN_HOLD (1 << 16) -#define BTN_MASK (BTN_VOL_DOWN | BTN_VOL_UP \ - | BTN_MENU | BTN_OFF ) - -#define SADC_CFG_INIT ( \ - (2 << SADC_CFG_CLKOUT_NUM_BIT) | \ - SADC_CFG_XYZ1Z2 | \ - SADC_CFG_SNUM_5 | \ - (1 << SADC_CFG_CLKDIV_BIT) | \ - SADC_CFG_PBAT_HIGH | \ - SADC_CFG_CMD_INT_PEN ) - -bool button_hold(void) -{ - return (REG_GPIO_PXPIN(3) ^ BTN_HOLD ? 1 : 0); -} - -void button_init_device(void) -{ - REG_SADC_ENA = 0; - REG_SADC_STATE &= (~REG_SADC_STATE); - REG_SADC_CTRL = 0x1f; - - __cpm_start_sadc(); - REG_SADC_CFG = SADC_CFG_INIT; - - REG_SADC_SAMETIME = 1; - REG_SADC_WAITTIME = 1000; //per 100 HZ - REG_SADC_STATE &= (~REG_SADC_STATE); - REG_SADC_CTRL &= (~(SADC_CTRL_PENDM | SADC_CTRL_TSRDYM)); - REG_SADC_ENA = SADC_ENA_TSEN; // | REG_SADC_ENA;//SADC_ENA_TSEN | SADC_ENA_PBATEN | SADC_ENA_SADCINEN; -} - -static int touch_to_pixels(short x, short y) -{ - /* X:300 -> 3800 Y:300->3900 */ - x -= 300; - y -= 300; - - x /= 3200 / LCD_WIDTH; - y /= 3600 / LCD_HEIGHT; - - return (x << 16) | y; -} - -int button_read_device(int *data) -{ - unsigned int key = ~REG_GPIO_PXPIN(3); - int ret = 0; - if(key & BTN_MASK) - { - if(key & BTN_VOL_DOWN) - ret |= BUTTON_VOL_DOWN; - if(key & BTN_VOL_UP) - ret |= BUTTON_VOL_UP; - if(key & BTN_MENU) - ret |= BUTTON_MENU; - if(key & BTN_OFF) - ret |= BUTTON_POWER; - } - - if(REG_SADC_STATE & (SADC_CTRL_TSRDYM|SADC_STATE_PEND)) - { - if(REG_SADC_STATE & SADC_CTRL_PENDM) - { - REG_SADC_CTRL &= (~(SADC_CTRL_PENUM | SADC_CTRL_TSRDYM)); - REG_SADC_CTRL |= (SADC_CTRL_PENDM); - unsigned int dat; - unsigned short xData,yData; - short tsz1Data,tsz2Data; - - dat = REG_SADC_TSDAT; - - xData = (dat >> 0) & 0xfff; - yData = (dat >> 16) & 0xfff; - - dat = REG_SADC_TSDAT; - tsz1Data = (dat >> 0) & 0xfff; - tsz2Data = (dat >> 16) & 0xfff; - - *data = touch_to_pixels(xData, yData); - - tsz1Data = tsz2Data - tsz1Data; - } - REG_SADC_STATE = 0; - //__intc_unmask_irq(IRQ_SADC); - } - - return ret; -} -void button_set_touch_available(void) -{ - return; -} +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2008 by Maurus Cuelenaere + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +#include "config.h" +#include "jz4740.h" +#include "button-target.h" + +#define BTN_VOL_DOWN (1 << 27) +#define BTN_VOL_UP (1 << 0) +#define BTN_MENU (1 << 1) +#define BTN_OFF (1 << 29) +#define BTN_HOLD (1 << 16) +#define BTN_MASK (BTN_VOL_DOWN | BTN_VOL_UP \ + | BTN_MENU | BTN_OFF ) + +#define SADC_CFG_INIT ( \ + (2 << SADC_CFG_CLKOUT_NUM_BIT) | \ + SADC_CFG_XYZ1Z2 | \ + SADC_CFG_SNUM_5 | \ + (1 << SADC_CFG_CLKDIV_BIT) | \ + SADC_CFG_PBAT_HIGH | \ + SADC_CFG_CMD_INT_PEN ) + +bool button_hold(void) +{ + return (REG_GPIO_PXPIN(3) ^ BTN_HOLD ? 1 : 0); +} + +void button_init_device(void) +{ + REG_SADC_ENA = 0; + REG_SADC_STATE &= (~REG_SADC_STATE); + REG_SADC_CTRL = 0x1f; + + __cpm_start_sadc(); + REG_SADC_CFG = SADC_CFG_INIT; + + REG_SADC_SAMETIME = 1; + REG_SADC_WAITTIME = 1000; //per 100 HZ + REG_SADC_STATE &= (~REG_SADC_STATE); + REG_SADC_CTRL &= (~(SADC_CTRL_PENDM | SADC_CTRL_TSRDYM)); + REG_SADC_ENA = SADC_ENA_TSEN; // | REG_SADC_ENA;//SADC_ENA_TSEN | SADC_ENA_PBATEN | SADC_ENA_SADCINEN; +} + +static int touch_to_pixels(short x, short y) +{ + /* X:300 -> 3800 Y:300->3900 */ + x -= 300; + y -= 300; + + x /= 3200 / LCD_WIDTH; + y /= 3600 / LCD_HEIGHT; + + return (x << 16) | y; +} + +int button_read_device(int *data) +{ + unsigned int key = ~REG_GPIO_PXPIN(3); + int ret = 0; + if(key & BTN_MASK) + { + if(key & BTN_VOL_DOWN) + ret |= BUTTON_VOL_DOWN; + if(key & BTN_VOL_UP) + ret |= BUTTON_VOL_UP; + if(key & BTN_MENU) + ret |= BUTTON_MENU; + if(key & BTN_OFF) + ret |= BUTTON_POWER; + } + + if(REG_SADC_STATE & (SADC_CTRL_TSRDYM|SADC_STATE_PEND)) + { + if(REG_SADC_STATE & SADC_CTRL_PENDM) + { + REG_SADC_CTRL &= (~(SADC_CTRL_PENUM | SADC_CTRL_TSRDYM)); + REG_SADC_CTRL |= (SADC_CTRL_PENDM); + unsigned int dat; + unsigned short xData,yData; + short tsz1Data,tsz2Data; + + dat = REG_SADC_TSDAT; + + xData = (dat >> 0) & 0xfff; + yData = (dat >> 16) & 0xfff; + + dat = REG_SADC_TSDAT; + tsz1Data = (dat >> 0) & 0xfff; + tsz2Data = (dat >> 16) & 0xfff; + + *data = touch_to_pixels(xData, yData); + + tsz1Data = tsz2Data - tsz1Data; + } + REG_SADC_STATE = 0; + //__intc_unmask_irq(IRQ_SADC); + } + + return ret; +} +void button_set_touch_available(void) +{ + return; +} -- cgit v1.2.3