From a1ab7a55ffc768da55e4cb30a87cfb85b1231902 Mon Sep 17 00:00:00 2001 From: Michael Sevakis Date: Thu, 4 Dec 2008 15:06:48 +0000 Subject: Meg-FX: s3c register definitions really should be unsigned. Switch from 'int' to 'unsigned long' like other targets. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19325 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/mmu-arm.c | 2 +- firmware/target/arm/s3c2440/debug-s3c2440.c | 51 +++++++++++----------- .../target/arm/s3c2440/gigabeat-fx/adc-meg-fx.c | 2 +- .../target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c | 12 ++--- .../target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c | 10 ++--- .../target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c | 18 ++++---- .../target/arm/s3c2440/gigabeat-fx/system-meg-fx.c | 19 ++++---- .../target/arm/s3c2440/gigabeat-fx/system-target.h | 7 +-- 8 files changed, 62 insertions(+), 59 deletions(-) (limited to 'firmware/target') diff --git a/firmware/target/arm/mmu-arm.c b/firmware/target/arm/mmu-arm.c index fff201cbfc..d86cd430b5 100644 --- a/firmware/target/arm/mmu-arm.c +++ b/firmware/target/arm/mmu-arm.c @@ -56,7 +56,7 @@ void __attribute__((naked)) map_section(unsigned int pa, unsigned int va, int mb : ); - register int *ttb_base asm ("r3") = TTB_BASE; /* force in r3 */ + register unsigned long *ttb_base asm ("r3") = TTB_BASE; /* force in r3 */ asm volatile ( diff --git a/firmware/target/arm/s3c2440/debug-s3c2440.c b/firmware/target/arm/s3c2440/debug-s3c2440.c index 97b7123a43..6c01f8bc1a 100644 --- a/firmware/target/arm/s3c2440/debug-s3c2440.c +++ b/firmware/target/arm/s3c2440/debug-s3c2440.c @@ -46,39 +46,40 @@ bool __dbg_ports(void) while(1) { line = 0; - snprintf(buf, sizeof(buf), "[Ports and Registers]"); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "[Ports and Registers]"); + lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "GPACON: %08x GPBCON: %08x", GPACON, GPBCON); lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "GPADAT: %08x GPBDAT: %08x", GPADAT, GPBDAT); lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "GPAUP: %08x GPBUP: %08x", 0, GPBUP); lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "GPCCON: %08x GPDCON: %08x", GPCCON, GPDCON); lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "GPCDAT: %08x GPDDAT: %08x", GPCDAT, GPDDAT); lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "GPCUP: %08x GPDUP: %08x", GPCUP, GPDUP); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "GPACON: %08lx GPBCON: %08lx", GPACON, GPBCON); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "GPADAT: %08lx GPBDAT: %08lx", GPADAT, GPBDAT); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "GPAUP: %08lx GPBUP: %08lx", 0ul, GPBUP); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "GPCCON: %08lx GPDCON: %08lx", GPCCON, GPDCON); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "GPCDAT: %08lx GPDDAT: %08lx", GPCDAT, GPDDAT); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "GPCUP: %08lx GPDUP: %08lx", GPCUP, GPDUP); lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "GPCCON: %08x GPDCON: %08x", GPCCON, GPDCON); lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "GPCDAT: %08x GPDDAT: %08x", GPCDAT, GPDDAT); lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "GPCUP: %08x GPDUP: %08x", GPCUP, GPDUP); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "GPCCON: %08lx GPDCON: %08lx", GPCCON, GPDCON); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "GPCDAT: %08lx GPDDAT: %08lx", GPCDAT, GPDDAT); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "GPCUP: %08lx GPDUP: %08lx", GPCUP, GPDUP); lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "GPECON: %08x GPFCON: %08x", GPECON, GPFCON); lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "GPEDAT: %08x GPFDAT: %08x", GPEDAT, GPFDAT); lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "GPEUP: %08x GPFUP: %08x", GPEUP, GPFUP); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "GPECON: %08lx GPFCON: %08lx", GPECON, GPFCON); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "GPEDAT: %08lx GPFDAT: %08lx", GPEDAT, GPFDAT); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "GPEUP: %08lx GPFUP: %08lx", GPEUP, GPFUP); lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "GPGCON: %08x GPHCON: %08x", GPGCON, GPHCON); lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "GPGDAT: %08x GPHDAT: %08x", GPGDAT, GPHDAT); lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "GPGUP: %08x GPHUP: %08x", GPGUP, GPHUP); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "GPGCON: %08lx GPHCON: %08lx", GPGCON, GPHCON); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "GPGDAT: %08lx GPHDAT: %08lx", GPGDAT, GPHDAT); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "GPGUP: %08lx GPHUP: %08lx", GPGUP, GPHUP); lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "GPJCON: %08x", GPJCON); lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "GPJDAT: %08x", GPJDAT); lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "GPJUP: %08x", GPJUP); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "GPJCON: %08lx", GPJCON); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "GPJDAT: %08lx", GPJDAT); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "GPJUP: %08lx", GPJUP); lcd_puts(0, line++, buf); line++; - snprintf(buf, sizeof(buf), "SRCPND: %08x INTMOD: %08x", SRCPND, INTMOD); lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "INTMSK: %08x INTPND: %08x", INTMSK, INTPND); lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "CLKCON: %08x CLKSLOW: %08x", CLKCON, CLKSLOW); lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "MPLLCON: %08x UPLLCON: %08x", MPLLCON, UPLLCON); lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "CLKDIVN: %08x CAMDIVN: %08x", CLKDIVN, CAMDIVN); lcd_puts(0, line++, buf); - snprintf(buf, sizeof(buf), "BWSCON: %08x TCONSEL: %08x", BWSCON, TCONSEL); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "SRCPND: %08lx INTMOD: %08lx", SRCPND, INTMOD); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "INTMSK: %08lx INTPND: %08lx", INTMSK, INTPND); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "CLKCON: %08lx CLKSLOW: %08lx", CLKCON, CLKSLOW); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "MPLLCON: %08lx UPLLCON: %08lx", MPLLCON, UPLLCON); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "CLKDIVN: %08lx CAMDIVN: %08lx", CLKDIVN, CAMDIVN); lcd_puts(0, line++, buf); + snprintf(buf, sizeof(buf), "BWSCON: %08lx TCONSEL: %08lx", BWSCON, TCONSEL); lcd_puts(0, line++, buf); lcd_update(); if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL)) diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/adc-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/adc-meg-fx.c index d821de4a30..fd5151a3bf 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/adc-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/adc-meg-fx.c @@ -35,7 +35,7 @@ void adc_init(void) int i; /* Turn on the ADC PCLK */ - s3c_regset(&CLKCON, 1<<15); + s3c_regset32(&CLKCON, 1<<15); /* Set channel 0, normal mode, disable "start by read" */ ADCCON &= ~(0x3F); diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c index 8300944243..836dedd462 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c @@ -43,7 +43,7 @@ void i2c_write(int addr, const unsigned char *buf, int count) mutex_lock(&i2c_mtx); /* Turn on I2C clock */ - s3c_regset(&CLKCON, 1 << 16); + s3c_regset32(&CLKCON, 1 << 16); /* Set mode to master transmitter and enable lines */ IICSTAT = I2C_MODE_MASTER | I2C_MODE_TX | I2C_RXTX_ENB; @@ -76,7 +76,7 @@ void i2c_write(int addr, const unsigned char *buf, int count) IICSTAT = 0; /* Turn off I2C clock */ - s3c_regclr(&CLKCON, 1 << 16); + s3c_regclr32(&CLKCON, 1 << 16); mutex_unlock(&i2c_mtx); } @@ -92,11 +92,11 @@ void i2c_init(void) INTPND = IIC_MASK; /* Enable i2c interrupt in controller */ - s3c_regclr(&INTMOD, IIC_MASK); - s3c_regclr(&INTMSK, IIC_MASK); + s3c_regclr32(&INTMOD, IIC_MASK); + s3c_regclr32(&INTMSK, IIC_MASK); /* Turn on I2C clock */ - s3c_regset(&CLKCON, 1 << 16); + s3c_regset32(&CLKCON, 1 << 16); /* Set GPE15 (IICSDA) and GPE14 (IICSCL) to IIC */ GPECON = (GPECON & ~((3 << 30) | (3 << 28))) | @@ -110,7 +110,7 @@ void i2c_init(void) IICLC = (0 << 0); /* Turn off I2C clock */ - s3c_regclr(&CLKCON, 1 << 16); + s3c_regclr32(&CLKCON, 1 << 16); } void IIC(void) diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c index ac8dc380e2..f3461cfe91 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/lcd-meg-fx.c @@ -103,7 +103,7 @@ static void LCD_CTRL_clock(bool onoff) GPDCON |= 0xAAA0AAA0; GPDUP |= 0xFCFC; - s3c_regset(&CLKCON, 0x20); /* enable LCD clock */ + s3c_regset32(&CLKCON, 0x20); /* enable LCD clock */ LCDCON1 |=0x01; } else @@ -115,7 +115,7 @@ static void LCD_CTRL_clock(bool onoff) GPDUP &= ~0xFCFC; LCDCON1 &= ~1; /* Must diable first or bus may freeze */ - s3c_regclr(&CLKCON, 0x20); /* disable LCD clock */ + s3c_regclr32(&CLKCON, 0x20); /* disable LCD clock */ } } @@ -162,7 +162,7 @@ static void LCD_SPI_SS(bool select) static void LCD_SPI_start(void) { - s3c_regset(&CLKCON, 0x40000); /* enable SPI clock */ + s3c_regset32(&CLKCON, 0x40000); /* enable SPI clock */ LCD_SPI_SS(false); SPCON0=0x3E; SPPRE0=24; @@ -176,7 +176,7 @@ static void LCD_SPI_stop(void) LCD_SPI_SS(false); SPCON0 &= ~0x10; - s3c_regclr(&CLKCON, 0x40000); /* disable SPI clock */ + s3c_regclr32(&CLKCON, 0x40000); /* disable SPI clock */ } static void LCD_SPI_powerdown(void) @@ -271,7 +271,7 @@ void lcd_init_device(void) GPBUP |= 0x181; - s3c_regset(&CLKCON, 0x20); /* enable LCD clock */ + s3c_regset32(&CLKCON, 0x20); /* enable LCD clock */ LCD_CTRL_setup(); LCD_SPI_init(); diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c index c219922607..14fbcd5cfe 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c @@ -77,14 +77,14 @@ void pcm_apply_settings(void) void pcm_play_lock(void) { if (++dma_play_lock.locked == 1) - s3c_regset(&INTMSK, DMA2_MASK); + s3c_regset32(&INTMSK, DMA2_MASK); } /* Unmask the DMA interrupt if enabled */ void pcm_play_unlock(void) { if (--dma_play_lock.locked == 0) - s3c_regclr(&INTMSK, dma_play_lock.state); + s3c_regclr32(&INTMSK, dma_play_lock.state); } void pcm_play_dma_init(void) @@ -94,7 +94,7 @@ void pcm_play_dma_init(void) /* There seem to be problems when changing the IIS interface configuration * when a clock is not present. */ - s3c_regset(&CLKCON, 1<<17); + s3c_regset32(&CLKCON, 1<<17); /* slave, transmit mode, 16 bit samples - MCLK 384fs - use 16.9344Mhz - BCLK 32fs */ IISMOD = (1<<9) | (1<<8) | (2<<6) | (1<<3) | (1<<2) | (1<<0); @@ -102,7 +102,7 @@ void pcm_play_dma_init(void) /* RX,TX off,on */ IISCON |= (1<<3) | (1<<2); - s3c_regclr(&CLKCON, 1<<17); + s3c_regclr32(&CLKCON, 1<<17); audiohw_init(); @@ -115,11 +115,11 @@ void pcm_play_dma_init(void) /* Do not service DMA requests, yet */ /* clear any pending int and mask it */ - s3c_regset(&INTMSK, DMA2_MASK); + s3c_regset32(&INTMSK, DMA2_MASK); SRCPND = DMA2_MASK; /* connect to FIQ */ - s3c_regset(&INTMOD, DMA2_MASK); + s3c_regset32(&INTMOD, DMA2_MASK); } void pcm_postinit(void) @@ -159,7 +159,7 @@ static void play_start_pcm(void) static void play_stop_pcm(void) { /* Mask DMA interrupt */ - s3c_regset(&INTMSK, DMA2_MASK); + s3c_regset32(&INTMSK, DMA2_MASK); /* De-Activate the DMA channel */ DMASKTRIG2 = 0x4; @@ -187,7 +187,7 @@ static void play_stop_pcm(void) void pcm_play_dma_start(const void *addr, size_t size) { /* Enable the IIS clock */ - s3c_regset(&CLKCON, 1<<17); + s3c_regset32(&CLKCON, 1<<17); /* stop any DMA in progress - idle IIS */ play_stop_pcm(); @@ -218,7 +218,7 @@ void pcm_play_dma_stop(void) play_stop_pcm(); /* Disconnect the IIS clock */ - s3c_regclr(&CLKCON, 1<<17); + s3c_regclr32(&CLKCON, 1<<17); } void pcm_play_dma_pause(bool pause) diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c index 8065926e28..6d8108be49 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/system-meg-fx.c @@ -118,34 +118,35 @@ static void set_page_tables(void) map_section((int)FRAME, (int)FRAME, 1, BUFFERED); /* enable buffered writing for the framebuffer */ } -void memory_init(void) { +void memory_init(void) +{ ttb_init(); set_page_tables(); enable_mmu(); } -void s3c_regmod(volatile int *reg, unsigned int set, unsigned int clr) +void s3c_regmod32(volatile unsigned long *reg, unsigned long bits, + unsigned long mask) { int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS); - unsigned int val = *reg; - *reg = (val | set) & ~clr; + *reg = (*reg & ~mask) | (bits & mask); restore_interrupt(oldstatus); } -void s3c_regset(volatile int *reg, unsigned int mask) +void s3c_regset32(volatile unsigned long *reg, unsigned long bits) { - s3c_regmod(reg, mask, 0); + s3c_regmod32(reg, bits, bits); } -void s3c_regclr(volatile int *reg, unsigned int mask) +void s3c_regclr32(volatile unsigned long *reg, unsigned long bits) { - s3c_regmod(reg, 0, mask); + s3c_regmod32(reg, 0, bits); } void system_init(void) { INTMSK = 0xFFFFFFFF; - INTMOD = 0; + INTMOD = 0; SRCPND = 0xFFFFFFFF; INTPND = 0xFFFFFFFF; INTSUBMSK = 0xFFFFFFFF; diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h b/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h index 46b726869b..43758ece08 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h +++ b/firmware/target/arm/s3c2440/gigabeat-fx/system-target.h @@ -31,11 +31,12 @@ /* Functions to set and clear regiser bits atomically */ /* Set and clear register bits */ -void s3c_regmod(volatile int *reg, unsigned int set, unsigned int clr); +void s3c_regmod32(volatile unsigned long *reg, unsigned long bits, + unsigned long mask); /* Set register bits */ -void s3c_regset(volatile int *reg, unsigned int mask); +void s3c_regset32(volatile unsigned long *reg, unsigned long bits); /* Clear register bits */ -void s3c_regclr(volatile int *reg, unsigned int mask); +void s3c_regclr32(volatile unsigned long *reg, unsigned long bits); #define HAVE_INVALIDATE_ICACHE static inline void invalidate_icache(void) -- cgit v1.2.3