From 7b861eca95b54f4132e2ed6a8f9c0edbf0a65ab8 Mon Sep 17 00:00:00 2001
From: Jens Arnold <amiconn@rockbox.org>
Date: Tue, 3 Jul 2007 00:42:42 +0000
Subject: More PP502x clock setup rework. This should fix the freezes on PP5020
 once and for all. Enabled clock scaling for H10. * CPUFREQ_MAX changed to
 78MHz * To be cleaned up soon.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13767 a1c6a512-1295-4272-9138-f99709370657
---
 firmware/target/arm/system-arm.h    |  8 ++++----
 firmware/target/arm/system-pp502x.c | 25 ++++++++++++++++++-------
 2 files changed, 22 insertions(+), 11 deletions(-)

(limited to 'firmware/target')

diff --git a/firmware/target/arm/system-arm.h b/firmware/target/arm/system-arm.h
index 26b8ac3513..99cab9e1a3 100644
--- a/firmware/target/arm/system-arm.h
+++ b/firmware/target/arm/system-arm.h
@@ -31,12 +31,12 @@
 #if CONFIG_CPU != S3C2440 && CONFIG_CPU != PNX0101
 
 /* TODO: Finish targeting this stuff */
-#define CPUFREQ_DEFAULT_MULT 8
+#define CPUFREQ_DEFAULT_MULT 4
 #define CPUFREQ_DEFAULT 24000000
-#define CPUFREQ_NORMAL_MULT 10
+#define CPUFREQ_NORMAL_MULT 5
 #define CPUFREQ_NORMAL 30000000
-#define CPUFREQ_MAX_MULT 25
-#define CPUFREQ_MAX 75000000
+#define CPUFREQ_MAX_MULT 13
+#define CPUFREQ_MAX 78000000
 
 #endif
 
diff --git a/firmware/target/arm/system-pp502x.c b/firmware/target/arm/system-pp502x.c
index 658ea0eeb3..4542913d53 100644
--- a/firmware/target/arm/system-pp502x.c
+++ b/firmware/target/arm/system-pp502x.c
@@ -152,6 +152,7 @@ static void ipod_init_cache(void)
 void set_cpu_frequency(long frequency)
 {
     unsigned long postmult, pll_control;
+    unsigned long unknown1, unknown2;
 
 # if NUM_CORES > 1
     /* Using mutex or spinlock isn't safe here. */
@@ -166,17 +167,25 @@ void set_cpu_frequency(long frequency)
         postmult = CPUFREQ_DEFAULT_MULT;
     cpu_frequency = frequency;
 
-    /* Enable PLL? */
-    outl(inl(0x70000020) | (1<<30), 0x70000020);
+    unknown2 = inl(0x600060a0);
 
-    /* Select 24MHz crystal as clock source? */
+    outl(inl(0x70000020) | (1<<30), 0x70000020);   /* Enable PLL power */
+
+    /* Set clock source #1 to 24MHz and select it */
     outl((inl(0x60006020) & 0x0ffffff0) | 0x10000002, 0x60006020);
+    
+    outl(unknown2 & 0x3fffffff, 0x600060a0);
+    
+    unknown1 = (138 * postmult + 255) >> 8;
+    if (unknown1 > 15)
+        unknown1 = 15;
+    outl((unknown1 << 8) | unknown1, 0x70000034);
 
-    /* Clock frequency = (24/8)*postmult */
-    pll_control = 0x8a020000 | 8 | (postmult << 8);
+    /* PLL frequency = (24/4)*postmult */
+    pll_control = 0x8a020000 | 4 | (postmult << 8);
     outl(pll_control, 0x60006034);
 # if CONFIG_CPU == PP5020
-    outl(0xd198, 0x6000603c);     /* magic sequence */
+    outl(0xd19b, 0x6000603c);     /* magic sequence */
     outl(pll_control, 0x60006034);
     udelay(500);                  /* wait for relock */
 # else /* PP5022, PP5024 */
@@ -186,6 +195,8 @@ void set_cpu_frequency(long frequency)
     /* Select PLL as clock source? */
     outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020);
     
+    outl(unknown2, 0x600060a0);
+    
 # if NUM_CORES > 1
     boostctrl_mtx.locked = 0;
 # endif
@@ -199,7 +210,7 @@ void ipod_set_cpu_frequency(void)
     outl(inl(0x70000020) | (1<<30), 0x70000020);
 
     /* Select 24MHz crystal as clock source? */
-    outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020);
+    outl((inl(0x60006020) & 0x0ffffff0) | 0x10000002, 0x60006020);
 
     /* Clock frequency = (24/8)*25 = 75MHz */
     outl(0x8a020000 | 8 | (25 << 8), 0x60006034);
-- 
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