From 3e9ca1de90ececc4f5c57058c565275823c0f800 Mon Sep 17 00:00:00 2001 From: Jens Arnold Date: Sun, 21 Sep 2008 22:32:56 +0000 Subject: Define the various CPUFREQ_* macros so that Gigabeat S compiles with test_codec enabled, and use the correct value. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18562 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/imx31/gigabeat-s/system-target.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'firmware/target') diff --git a/firmware/target/arm/imx31/gigabeat-s/system-target.h b/firmware/target/arm/imx31/gigabeat-s/system-target.h index 6438cde329..f25702eb4e 100644 --- a/firmware/target/arm/imx31/gigabeat-s/system-target.h +++ b/firmware/target/arm/imx31/gigabeat-s/system-target.h @@ -24,7 +24,12 @@ #include "system-arm.h" #include "mmu-arm.h" -#define CPUFREQ_NORMAL 532000000 +#ifndef HAVE_ADJUSTABLE_CPU_FREQ +/* TODO: implement CPU frequency scaling */ +#define CPUFREQ_DEFAULT CPU_FREQ +#define CPUFREQ_NORMAL CPU_FREQ +#define CPUFREQ_MAX CPU_FREQ +#endif #if 0 static inline void udelay(unsigned int usecs) @@ -49,7 +54,7 @@ static inline void invalidate_icache(void) asm volatile( /* Clean and invalidate entire data cache */ "mcr p15, 0, %0, c7, c14, 0 \n" - /* Invalidate entire intruction cache + /* Invalidate entire instruction cache * Also flushes the branch target cache */ "mcr p15, 0, %0, c7, c5, 0 \n" /* Data synchronization barrier */ -- cgit v1.2.3