From 06e9abc428fc5add36bebf9fed8a5a6353e41b21 Mon Sep 17 00:00:00 2001 From: William Wilgus Date: Sun, 30 Aug 2020 17:22:19 -0400 Subject: XduooX3 Tweak LCD drive strength and slew Change-Id: Ic5ee9e700a0c8acffc39b51cedc24ff44d230fd3 --- .../target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) (limited to 'firmware/target') diff --git a/firmware/target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c index ce8840f9d2..d4ab26ea5f 100644 --- a/firmware/target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c +++ b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c @@ -97,10 +97,20 @@ static inline void bitdelay(void) void lcd_hw_init(void) { - REG_GPIO_PXFUNC(2) = 0x000C73FC; /* D0-D7 RD DC CS RES WR */ - REG_GPIO_PXSELC(2) = 0x000C73FC; - REG_GPIO_PXDIRS(2) = 0x000C73FC; - REG_GPIO_PXDATS(2) = 0x000C73FC; + REG_GPIO_PXFUNC(2) = 0x000C73FC; /* D0-D7 RD DC CS RES WR -- GPIO/INTERRUPT */ + REG_GPIO_PXSELC(2) = 0x000C73FC; /* GPIO */ + + REG_GPIO_PXPEC(2) = 0x000C73FC; /* ENABLE PULLUP*/ + + REG_GPIO_PXDIRS(2) = 0x000C73FC; /* OUTPUT */ + REG_GPIO_PXDATS(2) = 0x000C73FC; /* D0-D7 RD DC CS RES WR -- SET BIT */ + + REG_GPIO_PXSLC(2) = 0x000C73FC; /* slew -- slow rate */ + + REG_GPIO_PXDS0C(2) = 0x000C73FC; /* Low pin drive strength */ + REG_GPIO_PXDS1C(2) = 0x000C73FC; + REG_GPIO_PXDS2C(2) = 0x000C73FC; + __gpio_clear_pin(PIN_BL_EN); __gpio_as_output(PIN_BL_EN); __gpio_clear_pin(PIN_LCD_RES); -- cgit v1.2.3