From 679a0bd19344eda0b0325831d950e6b5df63a6da Mon Sep 17 00:00:00 2001 From: Solomon Peachy Date: Thu, 30 Aug 2018 08:28:19 -0400 Subject: jz74x0: MSC clock needs to be divided from PLL clock. Change-Id: I0cf2f0d55e0859f896afef289e833935d7c5a599 --- firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c | 4 +++- firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c | 5 ++++- 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'firmware/target/mips') diff --git a/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c index 4de35367ba..f7754426b4 100644 --- a/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4740.c @@ -612,8 +612,10 @@ static inline unsigned int jz_sd_calc_clkrt(unsigned int rate) static inline void cpm_select_msc_clk(unsigned int rate) { unsigned int div = __cpm_get_pllout2() / rate; + if (div == 0) + div = 1; - REG_CPM_MSCCDR = div - 1; + REG_CPM_MSCCDR = MSCCDR_MCS | (div - 1); } /* Set the MMC clock frequency */ diff --git a/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c index a80e3ec919..93426157b7 100644 --- a/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c @@ -647,8 +647,11 @@ static inline unsigned int jz_sd_calc_clkrt(const int drive, unsigned int rate) static inline void cpm_select_msc_clk(unsigned int rate) { unsigned int div = __cpm_get_pllout2() / rate; + if (div == 0) + div = 1; - REG_CPM_MSCCDR = div - 1; + REG_CPM_MSCCDR = MSCCDR_MCS | (div - 1); + DEBUG("MSCCLK == %x\n", REG_CPM_MSCCDR); } /* Set the MMC clock frequency */ -- cgit v1.2.3