From 8cb4c18310f3975adfa318154b1b9c317fcdbfab Mon Sep 17 00:00:00 2001 From: Aidan MacDonald Date: Wed, 3 Mar 2021 23:48:49 +0000 Subject: Really fix the MIPS cache bug this time In fixing the original bug I tried to optimize discard_dcache_range() to minimize writeback and inadvertently introduced a second bug, which typically ends in a TLB refill panic. It occurs only if the range fits within one cache line, and when both the start and end of the range are not aligned to a cache line. This causes ptr to be incremented and end to be decremented, so ptr > end, and the loop can't terminate. Change-Id: Ibaac072f1369268d3327d534ad08ef9dcee3db65 --- firmware/target/mips/mmu-mips.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'firmware/target/mips/mmu-mips.c') diff --git a/firmware/target/mips/mmu-mips.c b/firmware/target/mips/mmu-mips.c index f4ffbfa6ee..46094bf6b6 100644 --- a/firmware/target/mips/mmu-mips.c +++ b/firmware/target/mips/mmu-mips.c @@ -235,7 +235,7 @@ void discard_dcache_range(const void *base, unsigned int size) } /* Interior of region is safe to discard */ - for(; ptr != end; ptr += CACHEALIGN_SIZE) + for(; ptr <= end; ptr += CACHEALIGN_SIZE) __CACHE_OP(DCHitInv, ptr); SYNC_WB(); -- cgit v1.2.3