From 3ec66893e377b088c1284d2d23adb2aeea6d7965 Mon Sep 17 00:00:00 2001 From: Aidan MacDonald Date: Sat, 27 Feb 2021 22:08:58 +0000 Subject: New port: FiiO M3K on bare metal Change-Id: I7517e7d5459e129dcfc9465c6fbd708619888fbe --- firmware/target/mips/ingenic_x1000/x1000/sfc.h | 481 +++++++++++++++++++++++++ 1 file changed, 481 insertions(+) create mode 100644 firmware/target/mips/ingenic_x1000/x1000/sfc.h (limited to 'firmware/target/mips/ingenic_x1000/x1000/sfc.h') diff --git a/firmware/target/mips/ingenic_x1000/x1000/sfc.h b/firmware/target/mips/ingenic_x1000/x1000/sfc.h new file mode 100644 index 0000000000..1a3c102c64 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/sfc.h @@ -0,0 +1,481 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * x1000 version: 1.0 + * x1000 authors: Aidan MacDonald + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_SFC_H__ +#define __HEADERGEN_SFC_H__ + +#include "macro.h" + +#define REG_SFC_GLB jz_reg(SFC_GLB) +#define JA_SFC_GLB (0xb3440000 + 0x0) +#define JT_SFC_GLB JIO_32_RW +#define JN_SFC_GLB SFC_GLB +#define JI_SFC_GLB +#define BP_SFC_GLB_THRESHOLD 7 +#define BM_SFC_GLB_THRESHOLD 0x1f80 +#define BF_SFC_GLB_THRESHOLD(v) (((v) & 0x3f) << 7) +#define BFM_SFC_GLB_THRESHOLD(v) BM_SFC_GLB_THRESHOLD +#define BF_SFC_GLB_THRESHOLD_V(e) BF_SFC_GLB_THRESHOLD(BV_SFC_GLB_THRESHOLD__##e) +#define BFM_SFC_GLB_THRESHOLD_V(v) BM_SFC_GLB_THRESHOLD +#define BP_SFC_GLB_PHASE_NUM 3 +#define BM_SFC_GLB_PHASE_NUM 0x38 +#define BF_SFC_GLB_PHASE_NUM(v) (((v) & 0x7) << 3) +#define BFM_SFC_GLB_PHASE_NUM(v) BM_SFC_GLB_PHASE_NUM +#define BF_SFC_GLB_PHASE_NUM_V(e) BF_SFC_GLB_PHASE_NUM(BV_SFC_GLB_PHASE_NUM__##e) +#define BFM_SFC_GLB_PHASE_NUM_V(v) BM_SFC_GLB_PHASE_NUM +#define BP_SFC_GLB_TRAN_DIR 13 +#define BM_SFC_GLB_TRAN_DIR 0x2000 +#define BV_SFC_GLB_TRAN_DIR__READ 0x0 +#define BV_SFC_GLB_TRAN_DIR__WRITE 0x1 +#define BF_SFC_GLB_TRAN_DIR(v) (((v) & 0x1) << 13) +#define BFM_SFC_GLB_TRAN_DIR(v) BM_SFC_GLB_TRAN_DIR +#define BF_SFC_GLB_TRAN_DIR_V(e) BF_SFC_GLB_TRAN_DIR(BV_SFC_GLB_TRAN_DIR__##e) +#define BFM_SFC_GLB_TRAN_DIR_V(v) BM_SFC_GLB_TRAN_DIR +#define BP_SFC_GLB_OP_MODE 6 +#define BM_SFC_GLB_OP_MODE 0x40 +#define BV_SFC_GLB_OP_MODE__SLAVE 0x0 +#define BV_SFC_GLB_OP_MODE__DMA 0x1 +#define BF_SFC_GLB_OP_MODE(v) (((v) & 0x1) << 6) +#define BFM_SFC_GLB_OP_MODE(v) BM_SFC_GLB_OP_MODE +#define BF_SFC_GLB_OP_MODE_V(e) BF_SFC_GLB_OP_MODE(BV_SFC_GLB_OP_MODE__##e) +#define BFM_SFC_GLB_OP_MODE_V(v) BM_SFC_GLB_OP_MODE +#define BP_SFC_GLB_WP_EN 2 +#define BM_SFC_GLB_WP_EN 0x4 +#define BF_SFC_GLB_WP_EN(v) (((v) & 0x1) << 2) +#define BFM_SFC_GLB_WP_EN(v) BM_SFC_GLB_WP_EN +#define BF_SFC_GLB_WP_EN_V(e) BF_SFC_GLB_WP_EN(BV_SFC_GLB_WP_EN__##e) +#define BFM_SFC_GLB_WP_EN_V(v) BM_SFC_GLB_WP_EN +#define BP_SFC_GLB_BURST_MD 0 +#define BM_SFC_GLB_BURST_MD 0x3 +#define BV_SFC_GLB_BURST_MD__INCR4 0x0 +#define BV_SFC_GLB_BURST_MD__INCR8 0x1 +#define BV_SFC_GLB_BURST_MD__INCR16 0x2 +#define BV_SFC_GLB_BURST_MD__INCR32 0x3 +#define BF_SFC_GLB_BURST_MD(v) (((v) & 0x3) << 0) +#define BFM_SFC_GLB_BURST_MD(v) BM_SFC_GLB_BURST_MD +#define BF_SFC_GLB_BURST_MD_V(e) BF_SFC_GLB_BURST_MD(BV_SFC_GLB_BURST_MD__##e) +#define BFM_SFC_GLB_BURST_MD_V(v) BM_SFC_GLB_BURST_MD + +#define REG_SFC_DEV_CONF jz_reg(SFC_DEV_CONF) +#define JA_SFC_DEV_CONF (0xb3440000 + 0x4) +#define JT_SFC_DEV_CONF JIO_32_RW +#define JN_SFC_DEV_CONF SFC_DEV_CONF +#define JI_SFC_DEV_CONF +#define BP_SFC_DEV_CONF_SMP_DELAY 16 +#define BM_SFC_DEV_CONF_SMP_DELAY 0x30000 +#define BF_SFC_DEV_CONF_SMP_DELAY(v) (((v) & 0x3) << 16) +#define BFM_SFC_DEV_CONF_SMP_DELAY(v) BM_SFC_DEV_CONF_SMP_DELAY +#define BF_SFC_DEV_CONF_SMP_DELAY_V(e) BF_SFC_DEV_CONF_SMP_DELAY(BV_SFC_DEV_CONF_SMP_DELAY__##e) +#define BFM_SFC_DEV_CONF_SMP_DELAY_V(v) BM_SFC_DEV_CONF_SMP_DELAY +#define BP_SFC_DEV_CONF_STA_TYPE 13 +#define BM_SFC_DEV_CONF_STA_TYPE 0x6000 +#define BV_SFC_DEV_CONF_STA_TYPE__1BYTE 0x0 +#define BV_SFC_DEV_CONF_STA_TYPE__2BYTE 0x1 +#define BV_SFC_DEV_CONF_STA_TYPE__3BYTE 0x2 +#define BV_SFC_DEV_CONF_STA_TYPE__4BYTE 0x3 +#define BF_SFC_DEV_CONF_STA_TYPE(v) (((v) & 0x3) << 13) +#define BFM_SFC_DEV_CONF_STA_TYPE(v) BM_SFC_DEV_CONF_STA_TYPE +#define BF_SFC_DEV_CONF_STA_TYPE_V(e) BF_SFC_DEV_CONF_STA_TYPE(BV_SFC_DEV_CONF_STA_TYPE__##e) +#define BFM_SFC_DEV_CONF_STA_TYPE_V(v) BM_SFC_DEV_CONF_STA_TYPE +#define BP_SFC_DEV_CONF_THOLD 11 +#define BM_SFC_DEV_CONF_THOLD 0x1800 +#define BF_SFC_DEV_CONF_THOLD(v) (((v) & 0x3) << 11) +#define BFM_SFC_DEV_CONF_THOLD(v) BM_SFC_DEV_CONF_THOLD +#define BF_SFC_DEV_CONF_THOLD_V(e) BF_SFC_DEV_CONF_THOLD(BV_SFC_DEV_CONF_THOLD__##e) +#define BFM_SFC_DEV_CONF_THOLD_V(v) BM_SFC_DEV_CONF_THOLD +#define BP_SFC_DEV_CONF_TSETUP 9 +#define BM_SFC_DEV_CONF_TSETUP 0x600 +#define BF_SFC_DEV_CONF_TSETUP(v) (((v) & 0x3) << 9) +#define BFM_SFC_DEV_CONF_TSETUP(v) BM_SFC_DEV_CONF_TSETUP +#define BF_SFC_DEV_CONF_TSETUP_V(e) BF_SFC_DEV_CONF_TSETUP(BV_SFC_DEV_CONF_TSETUP__##e) +#define BFM_SFC_DEV_CONF_TSETUP_V(v) BM_SFC_DEV_CONF_TSETUP +#define BP_SFC_DEV_CONF_TSH 5 +#define BM_SFC_DEV_CONF_TSH 0x1e0 +#define BF_SFC_DEV_CONF_TSH(v) (((v) & 0xf) << 5) +#define BFM_SFC_DEV_CONF_TSH(v) BM_SFC_DEV_CONF_TSH +#define BF_SFC_DEV_CONF_TSH_V(e) BF_SFC_DEV_CONF_TSH(BV_SFC_DEV_CONF_TSH__##e) +#define BFM_SFC_DEV_CONF_TSH_V(v) BM_SFC_DEV_CONF_TSH +#define BP_SFC_DEV_CONF_CMD_TYPE 15 +#define BM_SFC_DEV_CONF_CMD_TYPE 0x8000 +#define BV_SFC_DEV_CONF_CMD_TYPE__8BITS 0x0 +#define BV_SFC_DEV_CONF_CMD_TYPE__16BITS 0x1 +#define BF_SFC_DEV_CONF_CMD_TYPE(v) (((v) & 0x1) << 15) +#define BFM_SFC_DEV_CONF_CMD_TYPE(v) BM_SFC_DEV_CONF_CMD_TYPE +#define BF_SFC_DEV_CONF_CMD_TYPE_V(e) BF_SFC_DEV_CONF_CMD_TYPE(BV_SFC_DEV_CONF_CMD_TYPE__##e) +#define BFM_SFC_DEV_CONF_CMD_TYPE_V(v) BM_SFC_DEV_CONF_CMD_TYPE +#define BP_SFC_DEV_CONF_CPHA 4 +#define BM_SFC_DEV_CONF_CPHA 0x10 +#define BF_SFC_DEV_CONF_CPHA(v) (((v) & 0x1) << 4) +#define BFM_SFC_DEV_CONF_CPHA(v) BM_SFC_DEV_CONF_CPHA +#define BF_SFC_DEV_CONF_CPHA_V(e) BF_SFC_DEV_CONF_CPHA(BV_SFC_DEV_CONF_CPHA__##e) +#define BFM_SFC_DEV_CONF_CPHA_V(v) BM_SFC_DEV_CONF_CPHA +#define BP_SFC_DEV_CONF_CPOL 3 +#define BM_SFC_DEV_CONF_CPOL 0x8 +#define BF_SFC_DEV_CONF_CPOL(v) (((v) & 0x1) << 3) +#define BFM_SFC_DEV_CONF_CPOL(v) BM_SFC_DEV_CONF_CPOL +#define BF_SFC_DEV_CONF_CPOL_V(e) BF_SFC_DEV_CONF_CPOL(BV_SFC_DEV_CONF_CPOL__##e) +#define BFM_SFC_DEV_CONF_CPOL_V(v) BM_SFC_DEV_CONF_CPOL +#define BP_SFC_DEV_CONF_CE_DL 2 +#define BM_SFC_DEV_CONF_CE_DL 0x4 +#define BF_SFC_DEV_CONF_CE_DL(v) (((v) & 0x1) << 2) +#define BFM_SFC_DEV_CONF_CE_DL(v) BM_SFC_DEV_CONF_CE_DL +#define BF_SFC_DEV_CONF_CE_DL_V(e) BF_SFC_DEV_CONF_CE_DL(BV_SFC_DEV_CONF_CE_DL__##e) +#define BFM_SFC_DEV_CONF_CE_DL_V(v) BM_SFC_DEV_CONF_CE_DL +#define BP_SFC_DEV_CONF_HOLD_DL 1 +#define BM_SFC_DEV_CONF_HOLD_DL 0x2 +#define BF_SFC_DEV_CONF_HOLD_DL(v) (((v) & 0x1) << 1) +#define BFM_SFC_DEV_CONF_HOLD_DL(v) BM_SFC_DEV_CONF_HOLD_DL +#define BF_SFC_DEV_CONF_HOLD_DL_V(e) BF_SFC_DEV_CONF_HOLD_DL(BV_SFC_DEV_CONF_HOLD_DL__##e) +#define BFM_SFC_DEV_CONF_HOLD_DL_V(v) BM_SFC_DEV_CONF_HOLD_DL +#define BP_SFC_DEV_CONF_WP_DL 0 +#define BM_SFC_DEV_CONF_WP_DL 0x1 +#define BF_SFC_DEV_CONF_WP_DL(v) (((v) & 0x1) << 0) +#define BFM_SFC_DEV_CONF_WP_DL(v) BM_SFC_DEV_CONF_WP_DL +#define BF_SFC_DEV_CONF_WP_DL_V(e) BF_SFC_DEV_CONF_WP_DL(BV_SFC_DEV_CONF_WP_DL__##e) +#define BFM_SFC_DEV_CONF_WP_DL_V(v) BM_SFC_DEV_CONF_WP_DL + +#define REG_SFC_DEV_STA_EXP jz_reg(SFC_DEV_STA_EXP) +#define JA_SFC_DEV_STA_EXP (0xb3440000 + 0x8) +#define JT_SFC_DEV_STA_EXP JIO_32_RW +#define JN_SFC_DEV_STA_EXP SFC_DEV_STA_EXP +#define JI_SFC_DEV_STA_EXP + +#define REG_SFC_DEV_STA_RT jz_reg(SFC_DEV_STA_RT) +#define JA_SFC_DEV_STA_RT (0xb3440000 + 0xc) +#define JT_SFC_DEV_STA_RT JIO_32_RW +#define JN_SFC_DEV_STA_RT SFC_DEV_STA_RT +#define JI_SFC_DEV_STA_RT + +#define REG_SFC_DEV_STA_MSK jz_reg(SFC_DEV_STA_MSK) +#define JA_SFC_DEV_STA_MSK (0xb3440000 + 0x10) +#define JT_SFC_DEV_STA_MSK JIO_32_RW +#define JN_SFC_DEV_STA_MSK SFC_DEV_STA_MSK +#define JI_SFC_DEV_STA_MSK + +#define REG_SFC_TRAN_CONF(_n1) jz_reg(SFC_TRAN_CONF(_n1)) +#define JA_SFC_TRAN_CONF(_n1) (0xb3440000 + 0x14 + (_n1) * 0x4) +#define JT_SFC_TRAN_CONF(_n1) JIO_32_RW +#define JN_SFC_TRAN_CONF(_n1) SFC_TRAN_CONF +#define JI_SFC_TRAN_CONF(_n1) (_n1) +#define BP_SFC_TRAN_CONF_MODE 29 +#define BM_SFC_TRAN_CONF_MODE 0xe0000000 +#define BF_SFC_TRAN_CONF_MODE(v) (((v) & 0x7) << 29) +#define BFM_SFC_TRAN_CONF_MODE(v) BM_SFC_TRAN_CONF_MODE +#define BF_SFC_TRAN_CONF_MODE_V(e) BF_SFC_TRAN_CONF_MODE(BV_SFC_TRAN_CONF_MODE__##e) +#define BFM_SFC_TRAN_CONF_MODE_V(v) BM_SFC_TRAN_CONF_MODE +#define BP_SFC_TRAN_CONF_ADDR_WIDTH 26 +#define BM_SFC_TRAN_CONF_ADDR_WIDTH 0x1c000000 +#define BF_SFC_TRAN_CONF_ADDR_WIDTH(v) (((v) & 0x7) << 26) +#define BFM_SFC_TRAN_CONF_ADDR_WIDTH(v) BM_SFC_TRAN_CONF_ADDR_WIDTH +#define BF_SFC_TRAN_CONF_ADDR_WIDTH_V(e) BF_SFC_TRAN_CONF_ADDR_WIDTH(BV_SFC_TRAN_CONF_ADDR_WIDTH__##e) +#define BFM_SFC_TRAN_CONF_ADDR_WIDTH_V(v) BM_SFC_TRAN_CONF_ADDR_WIDTH +#define BP_SFC_TRAN_CONF_DUMMY_BITS 17 +#define BM_SFC_TRAN_CONF_DUMMY_BITS 0x7e0000 +#define BF_SFC_TRAN_CONF_DUMMY_BITS(v) (((v) & 0x3f) << 17) +#define BFM_SFC_TRAN_CONF_DUMMY_BITS(v) BM_SFC_TRAN_CONF_DUMMY_BITS +#define BF_SFC_TRAN_CONF_DUMMY_BITS_V(e) BF_SFC_TRAN_CONF_DUMMY_BITS(BV_SFC_TRAN_CONF_DUMMY_BITS__##e) +#define BFM_SFC_TRAN_CONF_DUMMY_BITS_V(v) BM_SFC_TRAN_CONF_DUMMY_BITS +#define BP_SFC_TRAN_CONF_COMMAND 0 +#define BM_SFC_TRAN_CONF_COMMAND 0xffff +#define BF_SFC_TRAN_CONF_COMMAND(v) (((v) & 0xffff) << 0) +#define BFM_SFC_TRAN_CONF_COMMAND(v) BM_SFC_TRAN_CONF_COMMAND +#define BF_SFC_TRAN_CONF_COMMAND_V(e) BF_SFC_TRAN_CONF_COMMAND(BV_SFC_TRAN_CONF_COMMAND__##e) +#define BFM_SFC_TRAN_CONF_COMMAND_V(v) BM_SFC_TRAN_CONF_COMMAND +#define BP_SFC_TRAN_CONF_POLL_EN 25 +#define BM_SFC_TRAN_CONF_POLL_EN 0x2000000 +#define BF_SFC_TRAN_CONF_POLL_EN(v) (((v) & 0x1) << 25) +#define BFM_SFC_TRAN_CONF_POLL_EN(v) BM_SFC_TRAN_CONF_POLL_EN +#define BF_SFC_TRAN_CONF_POLL_EN_V(e) BF_SFC_TRAN_CONF_POLL_EN(BV_SFC_TRAN_CONF_POLL_EN__##e) +#define BFM_SFC_TRAN_CONF_POLL_EN_V(v) BM_SFC_TRAN_CONF_POLL_EN +#define BP_SFC_TRAN_CONF_CMD_EN 24 +#define BM_SFC_TRAN_CONF_CMD_EN 0x1000000 +#define BF_SFC_TRAN_CONF_CMD_EN(v) (((v) & 0x1) << 24) +#define BFM_SFC_TRAN_CONF_CMD_EN(v) BM_SFC_TRAN_CONF_CMD_EN +#define BF_SFC_TRAN_CONF_CMD_EN_V(e) BF_SFC_TRAN_CONF_CMD_EN(BV_SFC_TRAN_CONF_CMD_EN__##e) +#define BFM_SFC_TRAN_CONF_CMD_EN_V(v) BM_SFC_TRAN_CONF_CMD_EN +#define BP_SFC_TRAN_CONF_PHASE_FMT 23 +#define BM_SFC_TRAN_CONF_PHASE_FMT 0x800000 +#define BF_SFC_TRAN_CONF_PHASE_FMT(v) (((v) & 0x1) << 23) +#define BFM_SFC_TRAN_CONF_PHASE_FMT(v) BM_SFC_TRAN_CONF_PHASE_FMT +#define BF_SFC_TRAN_CONF_PHASE_FMT_V(e) BF_SFC_TRAN_CONF_PHASE_FMT(BV_SFC_TRAN_CONF_PHASE_FMT__##e) +#define BFM_SFC_TRAN_CONF_PHASE_FMT_V(v) BM_SFC_TRAN_CONF_PHASE_FMT +#define BP_SFC_TRAN_CONF_DATA_EN 16 +#define BM_SFC_TRAN_CONF_DATA_EN 0x10000 +#define BF_SFC_TRAN_CONF_DATA_EN(v) (((v) & 0x1) << 16) +#define BFM_SFC_TRAN_CONF_DATA_EN(v) BM_SFC_TRAN_CONF_DATA_EN +#define BF_SFC_TRAN_CONF_DATA_EN_V(e) BF_SFC_TRAN_CONF_DATA_EN(BV_SFC_TRAN_CONF_DATA_EN__##e) +#define BFM_SFC_TRAN_CONF_DATA_EN_V(v) BM_SFC_TRAN_CONF_DATA_EN + +#define REG_SFC_TRAN_LENGTH jz_reg(SFC_TRAN_LENGTH) +#define JA_SFC_TRAN_LENGTH (0xb3440000 + 0x2c) +#define JT_SFC_TRAN_LENGTH JIO_32_RW +#define JN_SFC_TRAN_LENGTH SFC_TRAN_LENGTH +#define JI_SFC_TRAN_LENGTH + +#define REG_SFC_DEV_ADDR(_n1) jz_reg(SFC_DEV_ADDR(_n1)) +#define JA_SFC_DEV_ADDR(_n1) (0xb3440000 + 0x30 + (_n1) * 0x4) +#define JT_SFC_DEV_ADDR(_n1) JIO_32_RW +#define JN_SFC_DEV_ADDR(_n1) SFC_DEV_ADDR +#define JI_SFC_DEV_ADDR(_n1) (_n1) + +#define REG_SFC_DEV_PLUS(_n1) jz_reg(SFC_DEV_PLUS(_n1)) +#define JA_SFC_DEV_PLUS(_n1) (0xb3440000 + 0x48 + (_n1) * 0x40) +#define JT_SFC_DEV_PLUS(_n1) JIO_32_RW +#define JN_SFC_DEV_PLUS(_n1) SFC_DEV_PLUS +#define JI_SFC_DEV_PLUS(_n1) (_n1) + +#define REG_SFC_MEM_ADDR jz_reg(SFC_MEM_ADDR) +#define JA_SFC_MEM_ADDR (0xb3440000 + 0x60) +#define JT_SFC_MEM_ADDR JIO_32_RW +#define JN_SFC_MEM_ADDR SFC_MEM_ADDR +#define JI_SFC_MEM_ADDR + +#define REG_SFC_TRIG jz_reg(SFC_TRIG) +#define JA_SFC_TRIG (0xb3440000 + 0x64) +#define JT_SFC_TRIG JIO_32_RW +#define JN_SFC_TRIG SFC_TRIG +#define JI_SFC_TRIG +#define BP_SFC_TRIG_FLUSH 2 +#define BM_SFC_TRIG_FLUSH 0x4 +#define BF_SFC_TRIG_FLUSH(v) (((v) & 0x1) << 2) +#define BFM_SFC_TRIG_FLUSH(v) BM_SFC_TRIG_FLUSH +#define BF_SFC_TRIG_FLUSH_V(e) BF_SFC_TRIG_FLUSH(BV_SFC_TRIG_FLUSH__##e) +#define BFM_SFC_TRIG_FLUSH_V(v) BM_SFC_TRIG_FLUSH +#define BP_SFC_TRIG_STOP 1 +#define BM_SFC_TRIG_STOP 0x2 +#define BF_SFC_TRIG_STOP(v) (((v) & 0x1) << 1) +#define BFM_SFC_TRIG_STOP(v) BM_SFC_TRIG_STOP +#define BF_SFC_TRIG_STOP_V(e) BF_SFC_TRIG_STOP(BV_SFC_TRIG_STOP__##e) +#define BFM_SFC_TRIG_STOP_V(v) BM_SFC_TRIG_STOP +#define BP_SFC_TRIG_START 0 +#define BM_SFC_TRIG_START 0x1 +#define BF_SFC_TRIG_START(v) (((v) & 0x1) << 0) +#define BFM_SFC_TRIG_START(v) BM_SFC_TRIG_START +#define BF_SFC_TRIG_START_V(e) BF_SFC_TRIG_START(BV_SFC_TRIG_START__##e) +#define BFM_SFC_TRIG_START_V(v) BM_SFC_TRIG_START + +#define REG_SFC_SR jz_reg(SFC_SR) +#define JA_SFC_SR (0xb3440000 + 0x68) +#define JT_SFC_SR JIO_32_RW +#define JN_SFC_SR SFC_SR +#define JI_SFC_SR +#define BP_SFC_SR_FIFO_NUM 16 +#define BM_SFC_SR_FIFO_NUM 0x7f0000 +#define BF_SFC_SR_FIFO_NUM(v) (((v) & 0x7f) << 16) +#define BFM_SFC_SR_FIFO_NUM(v) BM_SFC_SR_FIFO_NUM +#define BF_SFC_SR_FIFO_NUM_V(e) BF_SFC_SR_FIFO_NUM(BV_SFC_SR_FIFO_NUM__##e) +#define BFM_SFC_SR_FIFO_NUM_V(v) BM_SFC_SR_FIFO_NUM +#define BP_SFC_SR_BUSY 5 +#define BM_SFC_SR_BUSY 0x60 +#define BF_SFC_SR_BUSY(v) (((v) & 0x3) << 5) +#define BFM_SFC_SR_BUSY(v) BM_SFC_SR_BUSY +#define BF_SFC_SR_BUSY_V(e) BF_SFC_SR_BUSY(BV_SFC_SR_BUSY__##e) +#define BFM_SFC_SR_BUSY_V(v) BM_SFC_SR_BUSY +#define BP_SFC_SR_END 4 +#define BM_SFC_SR_END 0x10 +#define BF_SFC_SR_END(v) (((v) & 0x1) << 4) +#define BFM_SFC_SR_END(v) BM_SFC_SR_END +#define BF_SFC_SR_END_V(e) BF_SFC_SR_END(BV_SFC_SR_END__##e) +#define BFM_SFC_SR_END_V(v) BM_SFC_SR_END +#define BP_SFC_SR_TREQ 3 +#define BM_SFC_SR_TREQ 0x8 +#define BF_SFC_SR_TREQ(v) (((v) & 0x1) << 3) +#define BFM_SFC_SR_TREQ(v) BM_SFC_SR_TREQ +#define BF_SFC_SR_TREQ_V(e) BF_SFC_SR_TREQ(BV_SFC_SR_TREQ__##e) +#define BFM_SFC_SR_TREQ_V(v) BM_SFC_SR_TREQ +#define BP_SFC_SR_RREQ 2 +#define BM_SFC_SR_RREQ 0x4 +#define BF_SFC_SR_RREQ(v) (((v) & 0x1) << 2) +#define BFM_SFC_SR_RREQ(v) BM_SFC_SR_RREQ +#define BF_SFC_SR_RREQ_V(e) BF_SFC_SR_RREQ(BV_SFC_SR_RREQ__##e) +#define BFM_SFC_SR_RREQ_V(v) BM_SFC_SR_RREQ +#define BP_SFC_SR_OVER 1 +#define BM_SFC_SR_OVER 0x2 +#define BF_SFC_SR_OVER(v) (((v) & 0x1) << 1) +#define BFM_SFC_SR_OVER(v) BM_SFC_SR_OVER +#define BF_SFC_SR_OVER_V(e) BF_SFC_SR_OVER(BV_SFC_SR_OVER__##e) +#define BFM_SFC_SR_OVER_V(v) BM_SFC_SR_OVER +#define BP_SFC_SR_UNDER 0 +#define BM_SFC_SR_UNDER 0x1 +#define BF_SFC_SR_UNDER(v) (((v) & 0x1) << 0) +#define BFM_SFC_SR_UNDER(v) BM_SFC_SR_UNDER +#define BF_SFC_SR_UNDER_V(e) BF_SFC_SR_UNDER(BV_SFC_SR_UNDER__##e) +#define BFM_SFC_SR_UNDER_V(v) BM_SFC_SR_UNDER + +#define REG_SFC_SCR jz_reg(SFC_SCR) +#define JA_SFC_SCR (0xb3440000 + 0x6c) +#define JT_SFC_SCR JIO_32_RW +#define JN_SFC_SCR SFC_SCR +#define JI_SFC_SCR +#define BP_SFC_SCR_CLR_END 4 +#define BM_SFC_SCR_CLR_END 0x10 +#define BF_SFC_SCR_CLR_END(v) (((v) & 0x1) << 4) +#define BFM_SFC_SCR_CLR_END(v) BM_SFC_SCR_CLR_END +#define BF_SFC_SCR_CLR_END_V(e) BF_SFC_SCR_CLR_END(BV_SFC_SCR_CLR_END__##e) +#define BFM_SFC_SCR_CLR_END_V(v) BM_SFC_SCR_CLR_END +#define BP_SFC_SCR_CLR_TREQ 3 +#define BM_SFC_SCR_CLR_TREQ 0x8 +#define BF_SFC_SCR_CLR_TREQ(v) (((v) & 0x1) << 3) +#define BFM_SFC_SCR_CLR_TREQ(v) BM_SFC_SCR_CLR_TREQ +#define BF_SFC_SCR_CLR_TREQ_V(e) BF_SFC_SCR_CLR_TREQ(BV_SFC_SCR_CLR_TREQ__##e) +#define BFM_SFC_SCR_CLR_TREQ_V(v) BM_SFC_SCR_CLR_TREQ +#define BP_SFC_SCR_CLR_RREQ 2 +#define BM_SFC_SCR_CLR_RREQ 0x4 +#define BF_SFC_SCR_CLR_RREQ(v) (((v) & 0x1) << 2) +#define BFM_SFC_SCR_CLR_RREQ(v) BM_SFC_SCR_CLR_RREQ +#define BF_SFC_SCR_CLR_RREQ_V(e) BF_SFC_SCR_CLR_RREQ(BV_SFC_SCR_CLR_RREQ__##e) +#define BFM_SFC_SCR_CLR_RREQ_V(v) BM_SFC_SCR_CLR_RREQ +#define BP_SFC_SCR_CLR_OVER 1 +#define BM_SFC_SCR_CLR_OVER 0x2 +#define BF_SFC_SCR_CLR_OVER(v) (((v) & 0x1) << 1) +#define BFM_SFC_SCR_CLR_OVER(v) BM_SFC_SCR_CLR_OVER +#define BF_SFC_SCR_CLR_OVER_V(e) BF_SFC_SCR_CLR_OVER(BV_SFC_SCR_CLR_OVER__##e) +#define BFM_SFC_SCR_CLR_OVER_V(v) BM_SFC_SCR_CLR_OVER +#define BP_SFC_SCR_CLR_UNDER 0 +#define BM_SFC_SCR_CLR_UNDER 0x1 +#define BF_SFC_SCR_CLR_UNDER(v) (((v) & 0x1) << 0) +#define BFM_SFC_SCR_CLR_UNDER(v) BM_SFC_SCR_CLR_UNDER +#define BF_SFC_SCR_CLR_UNDER_V(e) BF_SFC_SCR_CLR_UNDER(BV_SFC_SCR_CLR_UNDER__##e) +#define BFM_SFC_SCR_CLR_UNDER_V(v) BM_SFC_SCR_CLR_UNDER + +#define REG_SFC_INTC jz_reg(SFC_INTC) +#define JA_SFC_INTC (0xb3440000 + 0x70) +#define JT_SFC_INTC JIO_32_RW +#define JN_SFC_INTC SFC_INTC +#define JI_SFC_INTC +#define BP_SFC_INTC_MSK_END 4 +#define BM_SFC_INTC_MSK_END 0x10 +#define BF_SFC_INTC_MSK_END(v) (((v) & 0x1) << 4) +#define BFM_SFC_INTC_MSK_END(v) BM_SFC_INTC_MSK_END +#define BF_SFC_INTC_MSK_END_V(e) BF_SFC_INTC_MSK_END(BV_SFC_INTC_MSK_END__##e) +#define BFM_SFC_INTC_MSK_END_V(v) BM_SFC_INTC_MSK_END +#define BP_SFC_INTC_MSK_TREQ 3 +#define BM_SFC_INTC_MSK_TREQ 0x8 +#define BF_SFC_INTC_MSK_TREQ(v) (((v) & 0x1) << 3) +#define BFM_SFC_INTC_MSK_TREQ(v) BM_SFC_INTC_MSK_TREQ +#define BF_SFC_INTC_MSK_TREQ_V(e) BF_SFC_INTC_MSK_TREQ(BV_SFC_INTC_MSK_TREQ__##e) +#define BFM_SFC_INTC_MSK_TREQ_V(v) BM_SFC_INTC_MSK_TREQ +#define BP_SFC_INTC_MSK_RREQ 2 +#define BM_SFC_INTC_MSK_RREQ 0x4 +#define BF_SFC_INTC_MSK_RREQ(v) (((v) & 0x1) << 2) +#define BFM_SFC_INTC_MSK_RREQ(v) BM_SFC_INTC_MSK_RREQ +#define BF_SFC_INTC_MSK_RREQ_V(e) BF_SFC_INTC_MSK_RREQ(BV_SFC_INTC_MSK_RREQ__##e) +#define BFM_SFC_INTC_MSK_RREQ_V(v) BM_SFC_INTC_MSK_RREQ +#define BP_SFC_INTC_MSK_OVER 1 +#define BM_SFC_INTC_MSK_OVER 0x2 +#define BF_SFC_INTC_MSK_OVER(v) (((v) & 0x1) << 1) +#define BFM_SFC_INTC_MSK_OVER(v) BM_SFC_INTC_MSK_OVER +#define BF_SFC_INTC_MSK_OVER_V(e) BF_SFC_INTC_MSK_OVER(BV_SFC_INTC_MSK_OVER__##e) +#define BFM_SFC_INTC_MSK_OVER_V(v) BM_SFC_INTC_MSK_OVER +#define BP_SFC_INTC_MSK_UNDER 0 +#define BM_SFC_INTC_MSK_UNDER 0x1 +#define BF_SFC_INTC_MSK_UNDER(v) (((v) & 0x1) << 0) +#define BFM_SFC_INTC_MSK_UNDER(v) BM_SFC_INTC_MSK_UNDER +#define BF_SFC_INTC_MSK_UNDER_V(e) BF_SFC_INTC_MSK_UNDER(BV_SFC_INTC_MSK_UNDER__##e) +#define BFM_SFC_INTC_MSK_UNDER_V(v) BM_SFC_INTC_MSK_UNDER + +#define REG_SFC_FSM jz_reg(SFC_FSM) +#define JA_SFC_FSM (0xb3440000 + 0x74) +#define JT_SFC_FSM JIO_32_RW +#define JN_SFC_FSM SFC_FSM +#define JI_SFC_FSM +#define BP_SFC_FSM_STATE_AHB 16 +#define BM_SFC_FSM_STATE_AHB 0xf0000 +#define BF_SFC_FSM_STATE_AHB(v) (((v) & 0xf) << 16) +#define BFM_SFC_FSM_STATE_AHB(v) BM_SFC_FSM_STATE_AHB +#define BF_SFC_FSM_STATE_AHB_V(e) BF_SFC_FSM_STATE_AHB(BV_SFC_FSM_STATE_AHB__##e) +#define BFM_SFC_FSM_STATE_AHB_V(v) BM_SFC_FSM_STATE_AHB +#define BP_SFC_FSM_STATE_SPI 11 +#define BM_SFC_FSM_STATE_SPI 0xf800 +#define BF_SFC_FSM_STATE_SPI(v) (((v) & 0x1f) << 11) +#define BFM_SFC_FSM_STATE_SPI(v) BM_SFC_FSM_STATE_SPI +#define BF_SFC_FSM_STATE_SPI_V(e) BF_SFC_FSM_STATE_SPI(BV_SFC_FSM_STATE_SPI__##e) +#define BFM_SFC_FSM_STATE_SPI_V(v) BM_SFC_FSM_STATE_SPI +#define BP_SFC_FSM_STATE_CLK 6 +#define BM_SFC_FSM_STATE_CLK 0x3c0 +#define BF_SFC_FSM_STATE_CLK(v) (((v) & 0xf) << 6) +#define BFM_SFC_FSM_STATE_CLK(v) BM_SFC_FSM_STATE_CLK +#define BF_SFC_FSM_STATE_CLK_V(e) BF_SFC_FSM_STATE_CLK(BV_SFC_FSM_STATE_CLK__##e) +#define BFM_SFC_FSM_STATE_CLK_V(v) BM_SFC_FSM_STATE_CLK +#define BP_SFC_FSM_STATE_DMAC 3 +#define BM_SFC_FSM_STATE_DMAC 0x38 +#define BF_SFC_FSM_STATE_DMAC(v) (((v) & 0x7) << 3) +#define BFM_SFC_FSM_STATE_DMAC(v) BM_SFC_FSM_STATE_DMAC +#define BF_SFC_FSM_STATE_DMAC_V(e) BF_SFC_FSM_STATE_DMAC(BV_SFC_FSM_STATE_DMAC__##e) +#define BFM_SFC_FSM_STATE_DMAC_V(v) BM_SFC_FSM_STATE_DMAC +#define BP_SFC_FSM_STATE_RMC 0 +#define BM_SFC_FSM_STATE_RMC 0x7 +#define BF_SFC_FSM_STATE_RMC(v) (((v) & 0x7) << 0) +#define BFM_SFC_FSM_STATE_RMC(v) BM_SFC_FSM_STATE_RMC +#define BF_SFC_FSM_STATE_RMC_V(e) BF_SFC_FSM_STATE_RMC(BV_SFC_FSM_STATE_RMC__##e) +#define BFM_SFC_FSM_STATE_RMC_V(v) BM_SFC_FSM_STATE_RMC + +#define REG_SFC_CGE jz_reg(SFC_CGE) +#define JA_SFC_CGE (0xb3440000 + 0x78) +#define JT_SFC_CGE JIO_32_RW +#define JN_SFC_CGE SFC_CGE +#define JI_SFC_CGE +#define BP_SFC_CGE_SFC 5 +#define BM_SFC_CGE_SFC 0x20 +#define BF_SFC_CGE_SFC(v) (((v) & 0x1) << 5) +#define BFM_SFC_CGE_SFC(v) BM_SFC_CGE_SFC +#define BF_SFC_CGE_SFC_V(e) BF_SFC_CGE_SFC(BV_SFC_CGE_SFC__##e) +#define BFM_SFC_CGE_SFC_V(v) BM_SFC_CGE_SFC +#define BP_SFC_CGE_FIFO 4 +#define BM_SFC_CGE_FIFO 0x10 +#define BF_SFC_CGE_FIFO(v) (((v) & 0x1) << 4) +#define BFM_SFC_CGE_FIFO(v) BM_SFC_CGE_FIFO +#define BF_SFC_CGE_FIFO_V(e) BF_SFC_CGE_FIFO(BV_SFC_CGE_FIFO__##e) +#define BFM_SFC_CGE_FIFO_V(v) BM_SFC_CGE_FIFO +#define BP_SFC_CGE_DMA 3 +#define BM_SFC_CGE_DMA 0x8 +#define BF_SFC_CGE_DMA(v) (((v) & 0x1) << 3) +#define BFM_SFC_CGE_DMA(v) BM_SFC_CGE_DMA +#define BF_SFC_CGE_DMA_V(e) BF_SFC_CGE_DMA(BV_SFC_CGE_DMA__##e) +#define BFM_SFC_CGE_DMA_V(v) BM_SFC_CGE_DMA +#define BP_SFC_CGE_RMC 2 +#define BM_SFC_CGE_RMC 0x4 +#define BF_SFC_CGE_RMC(v) (((v) & 0x1) << 2) +#define BFM_SFC_CGE_RMC(v) BM_SFC_CGE_RMC +#define BF_SFC_CGE_RMC_V(e) BF_SFC_CGE_RMC(BV_SFC_CGE_RMC__##e) +#define BFM_SFC_CGE_RMC_V(v) BM_SFC_CGE_RMC +#define BP_SFC_CGE_SPI 1 +#define BM_SFC_CGE_SPI 0x2 +#define BF_SFC_CGE_SPI(v) (((v) & 0x1) << 1) +#define BFM_SFC_CGE_SPI(v) BM_SFC_CGE_SPI +#define BF_SFC_CGE_SPI_V(e) BF_SFC_CGE_SPI(BV_SFC_CGE_SPI__##e) +#define BFM_SFC_CGE_SPI_V(v) BM_SFC_CGE_SPI +#define BP_SFC_CGE_REG 0 +#define BM_SFC_CGE_REG 0x1 +#define BF_SFC_CGE_REG(v) (((v) & 0x1) << 0) +#define BFM_SFC_CGE_REG(v) BM_SFC_CGE_REG +#define BF_SFC_CGE_REG_V(e) BF_SFC_CGE_REG(BV_SFC_CGE_REG__##e) +#define BFM_SFC_CGE_REG_V(v) BM_SFC_CGE_REG + +#define REG_SFC_DATA jz_reg(SFC_DATA) +#define JA_SFC_DATA (0xb3440000 + 0x1000) +#define JT_SFC_DATA JIO_32_RW +#define JN_SFC_DATA SFC_DATA +#define JI_SFC_DATA + +#endif /* __HEADERGEN_SFC_H__*/ -- cgit v1.2.3