From f64e8dc33c83e41f5ce3917ba1c88bcfbbb6a3bf Mon Sep 17 00:00:00 2001 From: Aidan MacDonald Date: Sat, 29 May 2021 16:34:32 +0100 Subject: x1000: Complete the register definitions I think this covers everything now, although some fields are missing enum values. Those can be added in if and when they are needed. Change-Id: Ib1a94ba9c9a5949b6a038f8c1a49786823fae58f --- firmware/target/mips/ingenic_x1000/x1000/efuse.h | 173 +++++++++++++++++++++++ 1 file changed, 173 insertions(+) create mode 100644 firmware/target/mips/ingenic_x1000/x1000/efuse.h (limited to 'firmware/target/mips/ingenic_x1000/x1000/efuse.h') diff --git a/firmware/target/mips/ingenic_x1000/x1000/efuse.h b/firmware/target/mips/ingenic_x1000/x1000/efuse.h new file mode 100644 index 0000000000..8628cfd08b --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/efuse.h @@ -0,0 +1,173 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * x1000 version: 1.0 + * x1000 authors: Aidan MacDonald + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_EFUSE_H__ +#define __HEADERGEN_EFUSE_H__ + +#include "macro.h" + +#define REG_EFUSE_CTRL jz_reg(EFUSE_CTRL) +#define JA_EFUSE_CTRL (0xb3540000 + 0x0) +#define JT_EFUSE_CTRL JIO_32_RW +#define JN_EFUSE_CTRL EFUSE_CTRL +#define JI_EFUSE_CTRL +#define BP_EFUSE_CTRL_ADDR 21 +#define BM_EFUSE_CTRL_ADDR 0xfe00000 +#define BF_EFUSE_CTRL_ADDR(v) (((v) & 0x7f) << 21) +#define BFM_EFUSE_CTRL_ADDR(v) BM_EFUSE_CTRL_ADDR +#define BF_EFUSE_CTRL_ADDR_V(e) BF_EFUSE_CTRL_ADDR(BV_EFUSE_CTRL_ADDR__##e) +#define BFM_EFUSE_CTRL_ADDR_V(v) BM_EFUSE_CTRL_ADDR +#define BP_EFUSE_CTRL_LENGTH 16 +#define BM_EFUSE_CTRL_LENGTH 0x1f0000 +#define BF_EFUSE_CTRL_LENGTH(v) (((v) & 0x1f) << 16) +#define BFM_EFUSE_CTRL_LENGTH(v) BM_EFUSE_CTRL_LENGTH +#define BF_EFUSE_CTRL_LENGTH_V(e) BF_EFUSE_CTRL_LENGTH(BV_EFUSE_CTRL_LENGTH__##e) +#define BFM_EFUSE_CTRL_LENGTH_V(v) BM_EFUSE_CTRL_LENGTH +#define BP_EFUSE_CTRL_PG_EN 15 +#define BM_EFUSE_CTRL_PG_EN 0x8000 +#define BF_EFUSE_CTRL_PG_EN(v) (((v) & 0x1) << 15) +#define BFM_EFUSE_CTRL_PG_EN(v) BM_EFUSE_CTRL_PG_EN +#define BF_EFUSE_CTRL_PG_EN_V(e) BF_EFUSE_CTRL_PG_EN(BV_EFUSE_CTRL_PG_EN__##e) +#define BFM_EFUSE_CTRL_PG_EN_V(v) BM_EFUSE_CTRL_PG_EN +#define BP_EFUSE_CTRL_WR_EN 1 +#define BM_EFUSE_CTRL_WR_EN 0x2 +#define BF_EFUSE_CTRL_WR_EN(v) (((v) & 0x1) << 1) +#define BFM_EFUSE_CTRL_WR_EN(v) BM_EFUSE_CTRL_WR_EN +#define BF_EFUSE_CTRL_WR_EN_V(e) BF_EFUSE_CTRL_WR_EN(BV_EFUSE_CTRL_WR_EN__##e) +#define BFM_EFUSE_CTRL_WR_EN_V(v) BM_EFUSE_CTRL_WR_EN +#define BP_EFUSE_CTRL_RD_EN 0 +#define BM_EFUSE_CTRL_RD_EN 0x1 +#define BF_EFUSE_CTRL_RD_EN(v) (((v) & 0x1) << 0) +#define BFM_EFUSE_CTRL_RD_EN(v) BM_EFUSE_CTRL_RD_EN +#define BF_EFUSE_CTRL_RD_EN_V(e) BF_EFUSE_CTRL_RD_EN(BV_EFUSE_CTRL_RD_EN__##e) +#define BFM_EFUSE_CTRL_RD_EN_V(v) BM_EFUSE_CTRL_RD_EN + +#define REG_EFUSE_CFG jz_reg(EFUSE_CFG) +#define JA_EFUSE_CFG (0xb3540000 + 0x4) +#define JT_EFUSE_CFG JIO_32_RW +#define JN_EFUSE_CFG EFUSE_CFG +#define JI_EFUSE_CFG +#define BP_EFUSE_CFG_RD_AJD 20 +#define BM_EFUSE_CFG_RD_AJD 0x300000 +#define BF_EFUSE_CFG_RD_AJD(v) (((v) & 0x3) << 20) +#define BFM_EFUSE_CFG_RD_AJD(v) BM_EFUSE_CFG_RD_AJD +#define BF_EFUSE_CFG_RD_AJD_V(e) BF_EFUSE_CFG_RD_AJD(BV_EFUSE_CFG_RD_AJD__##e) +#define BFM_EFUSE_CFG_RD_AJD_V(v) BM_EFUSE_CFG_RD_AJD +#define BP_EFUSE_CFG_RD_STROBE 16 +#define BM_EFUSE_CFG_RD_STROBE 0x70000 +#define BF_EFUSE_CFG_RD_STROBE(v) (((v) & 0x7) << 16) +#define BFM_EFUSE_CFG_RD_STROBE(v) BM_EFUSE_CFG_RD_STROBE +#define BF_EFUSE_CFG_RD_STROBE_V(e) BF_EFUSE_CFG_RD_STROBE(BV_EFUSE_CFG_RD_STROBE__##e) +#define BFM_EFUSE_CFG_RD_STROBE_V(v) BM_EFUSE_CFG_RD_STROBE +#define BP_EFUSE_CFG_WR_ADJ 12 +#define BM_EFUSE_CFG_WR_ADJ 0x3000 +#define BF_EFUSE_CFG_WR_ADJ(v) (((v) & 0x3) << 12) +#define BFM_EFUSE_CFG_WR_ADJ(v) BM_EFUSE_CFG_WR_ADJ +#define BF_EFUSE_CFG_WR_ADJ_V(e) BF_EFUSE_CFG_WR_ADJ(BV_EFUSE_CFG_WR_ADJ__##e) +#define BFM_EFUSE_CFG_WR_ADJ_V(v) BM_EFUSE_CFG_WR_ADJ +#define BP_EFUSE_CFG_WR_STROBE 0 +#define BM_EFUSE_CFG_WR_STROBE 0x1ff +#define BF_EFUSE_CFG_WR_STROBE(v) (((v) & 0x1ff) << 0) +#define BFM_EFUSE_CFG_WR_STROBE(v) BM_EFUSE_CFG_WR_STROBE +#define BF_EFUSE_CFG_WR_STROBE_V(e) BF_EFUSE_CFG_WR_STROBE(BV_EFUSE_CFG_WR_STROBE__##e) +#define BFM_EFUSE_CFG_WR_STROBE_V(v) BM_EFUSE_CFG_WR_STROBE +#define BP_EFUSE_CFG_INT_EN 31 +#define BM_EFUSE_CFG_INT_EN 0x80000000 +#define BF_EFUSE_CFG_INT_EN(v) (((v) & 0x1) << 31) +#define BFM_EFUSE_CFG_INT_EN(v) BM_EFUSE_CFG_INT_EN +#define BF_EFUSE_CFG_INT_EN_V(e) BF_EFUSE_CFG_INT_EN(BV_EFUSE_CFG_INT_EN__##e) +#define BFM_EFUSE_CFG_INT_EN_V(v) BM_EFUSE_CFG_INT_EN + +#define REG_EFUSE_STATE jz_reg(EFUSE_STATE) +#define JA_EFUSE_STATE (0xb3540000 + 0x8) +#define JT_EFUSE_STATE JIO_32_RW +#define JN_EFUSE_STATE EFUSE_STATE +#define JI_EFUSE_STATE +#define BP_EFUSE_STATE_UK_PRT 23 +#define BM_EFUSE_STATE_UK_PRT 0x800000 +#define BF_EFUSE_STATE_UK_PRT(v) (((v) & 0x1) << 23) +#define BFM_EFUSE_STATE_UK_PRT(v) BM_EFUSE_STATE_UK_PRT +#define BF_EFUSE_STATE_UK_PRT_V(e) BF_EFUSE_STATE_UK_PRT(BV_EFUSE_STATE_UK_PRT__##e) +#define BFM_EFUSE_STATE_UK_PRT_V(v) BM_EFUSE_STATE_UK_PRT +#define BP_EFUSE_STATE_NKU_PRT 22 +#define BM_EFUSE_STATE_NKU_PRT 0x400000 +#define BF_EFUSE_STATE_NKU_PRT(v) (((v) & 0x1) << 22) +#define BFM_EFUSE_STATE_NKU_PRT(v) BM_EFUSE_STATE_NKU_PRT +#define BF_EFUSE_STATE_NKU_PRT_V(e) BF_EFUSE_STATE_NKU_PRT(BV_EFUSE_STATE_NKU_PRT__##e) +#define BFM_EFUSE_STATE_NKU_PRT_V(v) BM_EFUSE_STATE_NKU_PRT +#define BP_EFUSE_STATE_EXKEY_EN 21 +#define BM_EFUSE_STATE_EXKEY_EN 0x200000 +#define BF_EFUSE_STATE_EXKEY_EN(v) (((v) & 0x1) << 21) +#define BFM_EFUSE_STATE_EXKEY_EN(v) BM_EFUSE_STATE_EXKEY_EN +#define BF_EFUSE_STATE_EXKEY_EN_V(e) BF_EFUSE_STATE_EXKEY_EN(BV_EFUSE_STATE_EXKEY_EN__##e) +#define BFM_EFUSE_STATE_EXKEY_EN_V(v) BM_EFUSE_STATE_EXKEY_EN +#define BP_EFUSE_STATE_CUSTID_PRT 15 +#define BM_EFUSE_STATE_CUSTID_PRT 0x8000 +#define BF_EFUSE_STATE_CUSTID_PRT(v) (((v) & 0x1) << 15) +#define BFM_EFUSE_STATE_CUSTID_PRT(v) BM_EFUSE_STATE_CUSTID_PRT +#define BF_EFUSE_STATE_CUSTID_PRT_V(e) BF_EFUSE_STATE_CUSTID_PRT(BV_EFUSE_STATE_CUSTID_PRT__##e) +#define BFM_EFUSE_STATE_CUSTID_PRT_V(v) BM_EFUSE_STATE_CUSTID_PRT +#define BP_EFUSE_STATE_CHIPID_PRT 14 +#define BM_EFUSE_STATE_CHIPID_PRT 0x4000 +#define BF_EFUSE_STATE_CHIPID_PRT(v) (((v) & 0x1) << 14) +#define BFM_EFUSE_STATE_CHIPID_PRT(v) BM_EFUSE_STATE_CHIPID_PRT +#define BF_EFUSE_STATE_CHIPID_PRT_V(e) BF_EFUSE_STATE_CHIPID_PRT(BV_EFUSE_STATE_CHIPID_PRT__##e) +#define BFM_EFUSE_STATE_CHIPID_PRT_V(v) BM_EFUSE_STATE_CHIPID_PRT +#define BP_EFUSE_STATE_SECBOOT_PRT 12 +#define BM_EFUSE_STATE_SECBOOT_PRT 0x1000 +#define BF_EFUSE_STATE_SECBOOT_PRT(v) (((v) & 0x1) << 12) +#define BFM_EFUSE_STATE_SECBOOT_PRT(v) BM_EFUSE_STATE_SECBOOT_PRT +#define BF_EFUSE_STATE_SECBOOT_PRT_V(e) BF_EFUSE_STATE_SECBOOT_PRT(BV_EFUSE_STATE_SECBOOT_PRT__##e) +#define BFM_EFUSE_STATE_SECBOOT_PRT_V(v) BM_EFUSE_STATE_SECBOOT_PRT +#define BP_EFUSE_STATE_DIS_JTAG 11 +#define BM_EFUSE_STATE_DIS_JTAG 0x800 +#define BF_EFUSE_STATE_DIS_JTAG(v) (((v) & 0x1) << 11) +#define BFM_EFUSE_STATE_DIS_JTAG(v) BM_EFUSE_STATE_DIS_JTAG +#define BF_EFUSE_STATE_DIS_JTAG_V(e) BF_EFUSE_STATE_DIS_JTAG(BV_EFUSE_STATE_DIS_JTAG__##e) +#define BFM_EFUSE_STATE_DIS_JTAG_V(v) BM_EFUSE_STATE_DIS_JTAG +#define BP_EFUSE_STATE_SECBOOT_EN 8 +#define BM_EFUSE_STATE_SECBOOT_EN 0x100 +#define BF_EFUSE_STATE_SECBOOT_EN(v) (((v) & 0x1) << 8) +#define BFM_EFUSE_STATE_SECBOOT_EN(v) BM_EFUSE_STATE_SECBOOT_EN +#define BF_EFUSE_STATE_SECBOOT_EN_V(e) BF_EFUSE_STATE_SECBOOT_EN(BV_EFUSE_STATE_SECBOOT_EN__##e) +#define BFM_EFUSE_STATE_SECBOOT_EN_V(v) BM_EFUSE_STATE_SECBOOT_EN +#define BP_EFUSE_STATE_WR_DONE 1 +#define BM_EFUSE_STATE_WR_DONE 0x2 +#define BF_EFUSE_STATE_WR_DONE(v) (((v) & 0x1) << 1) +#define BFM_EFUSE_STATE_WR_DONE(v) BM_EFUSE_STATE_WR_DONE +#define BF_EFUSE_STATE_WR_DONE_V(e) BF_EFUSE_STATE_WR_DONE(BV_EFUSE_STATE_WR_DONE__##e) +#define BFM_EFUSE_STATE_WR_DONE_V(v) BM_EFUSE_STATE_WR_DONE +#define BP_EFUSE_STATE_RD_DONE 0 +#define BM_EFUSE_STATE_RD_DONE 0x1 +#define BF_EFUSE_STATE_RD_DONE(v) (((v) & 0x1) << 0) +#define BFM_EFUSE_STATE_RD_DONE(v) BM_EFUSE_STATE_RD_DONE +#define BF_EFUSE_STATE_RD_DONE_V(e) BF_EFUSE_STATE_RD_DONE(BV_EFUSE_STATE_RD_DONE__##e) +#define BFM_EFUSE_STATE_RD_DONE_V(v) BM_EFUSE_STATE_RD_DONE + +#define REG_EFUSE_DATA(_n1) jz_reg(EFUSE_DATA(_n1)) +#define JA_EFUSE_DATA(_n1) (0xb3540000 + 0xc + (_n1) * 0x4) +#define JT_EFUSE_DATA(_n1) JIO_32_RW +#define JN_EFUSE_DATA(_n1) EFUSE_DATA +#define JI_EFUSE_DATA(_n1) (_n1) + +#endif /* __HEADERGEN_EFUSE_H__*/ -- cgit v1.2.3