From f63edb52ef8ecf18520926b40b3c61db37081a9d Mon Sep 17 00:00:00 2001 From: Aidan MacDonald Date: Sun, 30 May 2021 19:56:44 +0100 Subject: x1000: refactor AIC initialization Have pcm-x1000 handle most work, so target's audiohw code touches only the relevant settings. Change-Id: Icf3d1b7ca428ac50a5a16ecec39ed8186ac5ae13 --- firmware/target/mips/ingenic_x1000/x1000/aic.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'firmware/target/mips/ingenic_x1000/x1000/aic.h') diff --git a/firmware/target/mips/ingenic_x1000/x1000/aic.h b/firmware/target/mips/ingenic_x1000/x1000/aic.h index d212ddc4e1..5f5e771c2c 100644 --- a/firmware/target/mips/ingenic_x1000/x1000/aic.h +++ b/firmware/target/mips/ingenic_x1000/x1000/aic.h @@ -123,18 +123,30 @@ #define JI_AIC_CCR #define BP_AIC_CCR_CHANNEL 24 #define BM_AIC_CCR_CHANNEL 0x7000000 +#define BV_AIC_CCR_CHANNEL__MONO 0x0 +#define BV_AIC_CCR_CHANNEL__STEREO 0x1 #define BF_AIC_CCR_CHANNEL(v) (((v) & 0x7) << 24) #define BFM_AIC_CCR_CHANNEL(v) BM_AIC_CCR_CHANNEL #define BF_AIC_CCR_CHANNEL_V(e) BF_AIC_CCR_CHANNEL(BV_AIC_CCR_CHANNEL__##e) #define BFM_AIC_CCR_CHANNEL_V(v) BM_AIC_CCR_CHANNEL #define BP_AIC_CCR_OSS 19 #define BM_AIC_CCR_OSS 0x380000 +#define BV_AIC_CCR_OSS__8BIT 0x0 +#define BV_AIC_CCR_OSS__16BIT 0x1 +#define BV_AIC_CCR_OSS__18BIT 0x2 +#define BV_AIC_CCR_OSS__20BIT 0x3 +#define BV_AIC_CCR_OSS__24BIT 0x4 #define BF_AIC_CCR_OSS(v) (((v) & 0x7) << 19) #define BFM_AIC_CCR_OSS(v) BM_AIC_CCR_OSS #define BF_AIC_CCR_OSS_V(e) BF_AIC_CCR_OSS(BV_AIC_CCR_OSS__##e) #define BFM_AIC_CCR_OSS_V(v) BM_AIC_CCR_OSS #define BP_AIC_CCR_ISS 16 #define BM_AIC_CCR_ISS 0x70000 +#define BV_AIC_CCR_ISS__8BIT 0x0 +#define BV_AIC_CCR_ISS__16BIT 0x1 +#define BV_AIC_CCR_ISS__18BIT 0x2 +#define BV_AIC_CCR_ISS__20BIT 0x3 +#define BV_AIC_CCR_ISS__24BIT 0x4 #define BF_AIC_CCR_ISS(v) (((v) & 0x7) << 16) #define BFM_AIC_CCR_ISS(v) BM_AIC_CCR_ISS #define BF_AIC_CCR_ISS_V(e) BF_AIC_CCR_ISS(BV_AIC_CCR_ISS__##e) -- cgit v1.2.3