From 3ec66893e377b088c1284d2d23adb2aeea6d7965 Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <amachronic@protonmail.com>
Date: Sat, 27 Feb 2021 22:08:58 +0000
Subject: New port: FiiO M3K on bare metal

Change-Id: I7517e7d5459e129dcfc9465c6fbd708619888fbe
---
 firmware/target/mips/ingenic_x1000/spl.lds | 47 ++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 firmware/target/mips/ingenic_x1000/spl.lds

(limited to 'firmware/target/mips/ingenic_x1000/spl.lds')

diff --git a/firmware/target/mips/ingenic_x1000/spl.lds b/firmware/target/mips/ingenic_x1000/spl.lds
new file mode 100644
index 0000000000..2a0b6b3eaa
--- /dev/null
+++ b/firmware/target/mips/ingenic_x1000/spl.lds
@@ -0,0 +1,47 @@
+#include "config.h"
+
+OUTPUT_FORMAT("elf32-littlemips")
+OUTPUT_ARCH(MIPS)
+ENTRY(_start)
+STARTUP(target/mips/ingenic_x1000/crt0.o)
+
+/* TCSM is 16 KiB and is mapped starting at address 0xf4000000.
+ *
+ * The SPL is loaded to TCSM + 0x1000. The area below that is stack space.
+ * The first 2 KiB of SPL is just headers. The code begins at TCSM + 0x1800.
+ * The maskrom will jump to that address (via jalr) after loading the SPL.
+ */
+MEMORY { TCSM : ORIGIN = 0xf4001800, LENGTH = 0x2800 }
+
+SECTIONS
+{
+    .text :
+    {
+        *(.init.text);
+        *(.text*);
+    } > TCSM
+
+    . = ALIGN(4);
+    .rodata :
+    {
+        *(.rodata*);
+    } > TCSM
+
+    . = ALIGN(4);
+    .data :
+    {
+        *(.data*);
+        *(.sdata*);
+    } > TCSM
+
+    . = ALIGN(4);
+    .bss (NOLOAD) :
+    {
+        _bssbegin = .;
+        *(.sbss*);
+        *(.bss*);
+        *(COMMON);
+        *(.scommon*);
+        _bssend = .;
+    } > TCSM
+}
-- 
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