From 01d1eb425874813864d12d72c93e6e74ab92ac1f Mon Sep 17 00:00:00 2001 From: Aidan MacDonald Date: Thu, 15 Apr 2021 03:00:04 +0100 Subject: FiiO M3K/X1000: Do system clock initialization in the SPL Initializing the clocks in the SPL brings Rockbox in line with how the FiiO M3K's original SPL works. It's likely other X1000 devices do this too. There was a logic error in the previous setup: the code falsely assumed that DDR memory would always be running from MPLL, but it would be switched to APLL by the bootloader. Rockbox would then try to re-init APLL, albeit with the same parameters. Maybe this was the cause of the boot hang on some units. Change-Id: I64064585e491bbdf1e95fe9428c91a9314f2a917 --- firmware/target/mips/ingenic_x1000/spl-x1000.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'firmware/target/mips/ingenic_x1000/spl-x1000.c') diff --git a/firmware/target/mips/ingenic_x1000/spl-x1000.c b/firmware/target/mips/ingenic_x1000/spl-x1000.c index 59e0fb687d..e6d87066b5 100644 --- a/firmware/target/mips/ingenic_x1000/spl-x1000.c +++ b/firmware/target/mips/ingenic_x1000/spl-x1000.c @@ -279,7 +279,8 @@ void main(void) if(nandread(opt->nand_addr, opt->nand_size, (void*)opt->load_addr)) spl_error(); - /* TODO: implement dual boot */ + /* Let target handle necessary pre-boot setup */ + spl_handle_pre_boot(option); /* Reading the Linux command line from the bootloader is handled by * arch/mips/xburst/core/prom.c -- see Ingenic kernel sources. -- cgit v1.2.3