From b5558c1cf968f0fcff072456408b14f130f29ce3 Mon Sep 17 00:00:00 2001 From: amachronic Date: Mon, 5 Apr 2021 13:21:42 +0100 Subject: x1000: place SPL's NAND bounce buffers in DRAM This frees up 2 KiB in the SPL's memory map, leaving more room for code. Change-Id: I01bbe2ab2905b2773a8b76d8c53e9f3d55bd040f --- firmware/target/mips/ingenic_x1000/nand-x1000.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'firmware/target/mips/ingenic_x1000/nand-x1000.c') diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.c b/firmware/target/mips/ingenic_x1000/nand-x1000.c index 54a1d11d95..df86bebf4d 100644 --- a/firmware/target/mips/ingenic_x1000/nand-x1000.c +++ b/firmware/target/mips/ingenic_x1000/nand-x1000.c @@ -40,11 +40,15 @@ /* Defined by target */ extern const nand_chip_desc target_nand_chip_descs[]; -/* Globals for the driver - * TODO: get rid of pagebuffer in the SPL to save code size - */ -static unsigned char pagebuffer[NAND_MAX_PAGE_SIZE] CACHEALIGN_ATTR; -static unsigned char auxbuffer[NAND_AUX_BUFFER_SIZE] CACHEALIGN_ATTR; +#ifdef BOOTLOADER_SPL +# define NANDBUFFER_ATTR __attribute__((section(".sdram"))) CACHEALIGN_ATTR +#else +# define NANDBUFFER_ATTR CACHEALIGN_ATTR +#endif + +/* Globals for the driver */ +static unsigned char pagebuffer[NAND_MAX_PAGE_SIZE] NANDBUFFER_ATTR; +static unsigned char auxbuffer[NAND_AUX_BUFFER_SIZE] NANDBUFFER_ATTR; static nand_drv nand_driver; static void nand_drv_reset(nand_drv* d) -- cgit v1.2.3