From 1b8542490da3283dfa0ce0f3363f16eab0609815 Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <amachronic@protonmail.com>
Date: Wed, 7 Apr 2021 22:11:01 +0100
Subject: x1000: Redesign SPL, and allow it to flash the bootloader

SPL is now designed so core X1000 code is in control of the boot,
under the reasonable assumption that the device boots from flash.
It should not be too hard to adapt to other X1000 ports.

The biggest functional change is that the SPL can now read/write
the flash, under the control of a host computer. The SPL relies
on the boot ROM for USB communication, so the host has to execute
the SPL multiple times following a protocol.

Change-Id: I3ffaa00e4bf191e043c9df0e2e64d15193ff42c9
---
 .../mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c       | 132 +++++++++++++++++++++
 1 file changed, 132 insertions(+)
 create mode 100644 firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c

(limited to 'firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c')

diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c b/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c
new file mode 100644
index 0000000000..0ebe11e24d
--- /dev/null
+++ b/firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c
@@ -0,0 +1,132 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2021 Aidan MacDonald
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "spl-x1000.h"
+#include "gpio-x1000.h"
+#include "nand-x1000.h"
+#include "system.h"
+#include <string.h>
+
+/* Boot select button state must remain stable for this duration
+ * before the choice will be accepted. Currently 100ms.
+ */
+#define BTN_STABLE_TIME (100 * (X1000_EXCLK_FREQ / 4000))
+
+static const char normal_cmdline[] = "mem=64M@0x0\
+ no_console_suspend\
+ console=ttyS2,115200n8\
+ lpj=5009408\
+ ip=off\
+ init=/linuxrc\
+ ubi.mtd=3\
+ root=ubi0:rootfs\
+ ubi.mtd=4\
+ rootfstype=ubifs\
+ rw\
+ loglevel=8";
+
+static const char recovery_cmdline[] = "mem=64M@0x0\
+ no_console_suspend\
+ console=ttyS2,115200n8\
+ lpj=5009408\
+ ip=off";
+
+const struct spl_boot_option spl_boot_options[] = {
+    {
+        /* Rockbox: the first unused NAND page is 26 KiB in, and the
+         * remainder of the block is unused, giving us 102 KiB to use.
+         */
+        .nand_addr = 0x6800,
+        .nand_size = 0x19800,
+        .load_addr = 0x80003ff8, /* first 8 bytes are bootloader ID */
+        .exec_addr = 0x80004000,
+        .cmdline = NULL,
+    },
+    {
+        /* Original firmware */
+        .nand_addr = 0x20000,
+        .nand_size = 0x400000,
+        .load_addr = 0x80efffc0,
+        .exec_addr = 0x80f00000,
+        .cmdline = normal_cmdline,
+    },
+    {
+        /* Recovery image */
+        .nand_addr = 0x420000,
+        .nand_size = 0x500000,
+        .load_addr = 0x80efffc0,
+        .exec_addr = 0x80f00000,
+        .cmdline = recovery_cmdline,
+    },
+};
+
+void spl_error(void)
+{
+    const int pin = (1 << 24);
+
+    /* Turn on button light */
+    jz_clr(GPIO_INT(GPIO_C), pin);
+    jz_set(GPIO_MSK(GPIO_C), pin);
+    jz_clr(GPIO_PAT1(GPIO_C), pin);
+    jz_set(GPIO_PAT0(GPIO_C), pin);
+
+    while(1) {
+        /* Turn it off */
+        mdelay(100);
+        jz_set(GPIO_PAT0(GPIO_C), pin);
+
+        /* Turn it on */
+        mdelay(100);
+        jz_clr(GPIO_PAT0(GPIO_C), pin);
+    }
+}
+
+int spl_get_boot_option(void)
+{
+    const uint32_t pinmask = (1 << 17) | (1 << 19);
+
+    uint32_t pin = 1, lastpin = 0;
+    uint32_t deadline = 0;
+
+    /* Configure the button GPIOs as inputs */
+    gpio_config(GPIO_A, pinmask, GPIO_INPUT);
+
+    /* Poll the pins for a short duration to detect a keypress */
+    do {
+        lastpin = pin;
+        pin = ~REG_GPIO_PIN(GPIO_A) & pinmask;
+        if(pin != lastpin) {
+            /* This will always be set on the first iteration */
+            deadline = __ost_read32() + BTN_STABLE_TIME;
+        }
+    } while(__ost_read32() < deadline);
+
+    /* Play button boots original firmware */
+    if(pin == (1 << 17))
+        return SPL_BOOTOPT_ORIG_FW;
+
+    /* Volume up boots recovery */
+    if(pin == (1 << 19))
+        return SPL_BOOTOPT_RECOVERY;
+
+    /* Default is to boot Rockbox */
+    return SPL_BOOTOPT_ROCKBOX;
+}
-- 
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