From 0cb162a76b16d58250a33e817af6a763e89a770a Mon Sep 17 00:00:00 2001 From: Solomon Peachy Date: Fri, 28 Aug 2020 21:45:58 -0400 Subject: mips: Heavily rework DMA & caching code Based on code originally written by Amaury Pouly (g#1789, g#1791, g#1527) but rebased and heavily updated. Change-Id: Ic794abb5e8d89feb4b88fc3abe854270fb28db70 --- firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c') diff --git a/firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c b/firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c index 83d3646ed1..00a2b22591 100644 --- a/firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c @@ -69,6 +69,8 @@ static inline void set_dma(const void *addr, size_t size) int burst_size; logf("%x %d %x", (unsigned int)addr, size, REG_AIC_SR); + commit_discard_dcache_range(addr, size); + if(size % 16) { if(size % 4) @@ -88,7 +90,6 @@ static inline void set_dma(const void *addr, size_t size) burst_size = DMAC_DCMD_DS_16BYTE; } - __dcache_writeback_all(); REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) = DMAC_DCCSR_NDES; REG_DMAC_DSAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)addr); REG_DMAC_DTAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)AIC_DR); -- cgit v1.2.3