From 3867f0b95958a6219ed5b459c22b246fb827efe2 Mon Sep 17 00:00:00 2001 From: William Wilgus Date: Sat, 29 Aug 2020 10:14:03 -0400 Subject: XduooX3 Sources WS changes Change-Id: I17ae59e7ef0440756527ce50ab30f8bf34f79007 --- .../target/mips/ingenic_jz47xx/ata-nand-jz4740.c | 104 ++++++++++----------- 1 file changed, 52 insertions(+), 52 deletions(-) (limited to 'firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c') diff --git a/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c b/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c index 1ae3bb2cc8..a582db82cc 100644 --- a/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c @@ -149,20 +149,20 @@ static inline void jz_nand_read_buf8(void *buf, int count) static void jz_nand_write_dma(void *source, unsigned int len, int bw) { mutex_lock(&nand_dma_mtx); - + if(((unsigned int)source < 0xa0000000) && len) dma_cache_wback_inv((unsigned long)source, len); - + dma_enable(); REG_DMAC_DCCSR(DMA_NAND_CHANNEL) = DMAC_DCCSR_NDES; - REG_DMAC_DSAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)source); - REG_DMAC_DTAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)NAND_DATAPORT); - REG_DMAC_DTCR(DMA_NAND_CHANNEL) = len / 16; - REG_DMAC_DRSR(DMA_NAND_CHANNEL) = DMAC_DRSR_RS_AUTO; + REG_DMAC_DSAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)source); + REG_DMAC_DTAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)NAND_DATAPORT); + REG_DMAC_DTCR(DMA_NAND_CHANNEL) = len / 16; + REG_DMAC_DRSR(DMA_NAND_CHANNEL) = DMAC_DRSR_RS_AUTO; REG_DMAC_DCMD(DMA_NAND_CHANNEL) = (DMAC_DCMD_SAI| DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_16BYTE | (bw == 8 ? DMAC_DCMD_DWDH_8 : DMAC_DCMD_DWDH_16)); - + REG_DMAC_DCCSR(DMA_NAND_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */ #if 1 while( REG_DMAC_DTCR(DMA_NAND_CHANNEL) ) @@ -173,26 +173,26 @@ static void jz_nand_write_dma(void *source, unsigned int len, int bw) #endif REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */ - + dma_disable(); - + mutex_unlock(&nand_dma_mtx); } static void jz_nand_read_dma(void *target, unsigned int len, int bw) { mutex_lock(&nand_dma_mtx); - + if(((unsigned int)target < 0xa0000000) && len) dma_cache_wback_inv((unsigned long)target, len); dma_enable(); - + REG_DMAC_DCCSR(DMA_NAND_CHANNEL) = DMAC_DCCSR_NDES ; - REG_DMAC_DSAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)NAND_DATAPORT); - REG_DMAC_DTAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)target); - REG_DMAC_DTCR(DMA_NAND_CHANNEL) = len / 4; - REG_DMAC_DRSR(DMA_NAND_CHANNEL) = DMAC_DRSR_RS_AUTO; + REG_DMAC_DSAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)NAND_DATAPORT); + REG_DMAC_DTAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)target); + REG_DMAC_DTCR(DMA_NAND_CHANNEL) = len / 4; + REG_DMAC_DRSR(DMA_NAND_CHANNEL) = DMAC_DRSR_RS_AUTO; REG_DMAC_DCMD(DMA_NAND_CHANNEL) = (DMAC_DCMD_SAI| DMAC_DCMD_DAI | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT | (bw == 8 ? DMAC_DCMD_SWDH_8 : DMAC_DCMD_SWDH_16)); REG_DMAC_DCCSR(DMA_NAND_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */ @@ -205,9 +205,9 @@ static void jz_nand_read_dma(void *target, unsigned int len, int bw) #endif //REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */ - + dma_disable(); - + mutex_unlock(&nand_dma_mtx); } @@ -224,7 +224,7 @@ void DMA_CALLBACK(DMA_NAND_CHANNEL)(void) if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_TT) REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_TT; - + semaphore_release(&nand_dma_complete); } #endif /* USE_DMA */ @@ -246,7 +246,7 @@ static inline void jz_nand_read_buf(void *buf, int count, int bw) #ifdef USE_ECC /* - * Correct 1~9-bit errors in 512-bytes data + * Correct 1~9-bit errors in 512-bytes data */ static void jz_rs_correct(unsigned char *dat, int idx, int mask) { @@ -349,7 +349,7 @@ static int jz_nand_read_page(unsigned long page_addr, unsigned char *dst) #endif unsigned char *data_buf; unsigned char oob_buf[nandp->oob_size]; - + if(nand_address == 0) return -1; @@ -484,28 +484,28 @@ static void jz_nand_disable(void) * Enable NAND controller */ static void jz_nand_enable(void) -{ +{ #if 0 /* OF RE */ REG_GPIO_PXFUNS(1) = 0x1E018000; // __gpio_as_func0() start REG_GPIO_PXSELC(1) = 0x1E018000; // __gpio_as_func0() end - + REG_GPIO_PXFUNS(2) = 0x3000<<16; // __gpio_as_func0() start REG_GPIO_PXSELC(2) = 0x3000<<16; // __gpio_as_func0() end - + REG_GPIO_PXFUNC(2) = 0x4000<<16; // __gpio_port_as_input() start REG_GPIO_PXSELC(2) = 0x4000<<16; REG_GPIO_PXDIRC(2) = 0x4000<<16; // __gpio_port_as_input() end REG_GPIO_PXPES(2) = 0x4000<<16; // __gpio_disable_pull() - + REG_GPIO_PXFUNS(1) = 0x40<<16; // __gpio_as_func0() start REG_GPIO_PXSELC(1) = 0x40<<16; // __gpio_as_func0() end - + REG_EMC_SMCR1 = (REG_EMC_SMCR1 & 0xFF) | 0x4621200; REG_EMC_SMCR2 = (REG_EMC_SMCR2 & 0xFF) | 0x4621200; REG_EMC_SMCR3 = (REG_EMC_SMCR3 & 0xFF) | 0x4621200; REG_EMC_SMCR4 = (REG_EMC_SMCR4 & 0xFF) | 0x4621200; - + REG_EMC_SMCR1 = REG_EMC_SMCR2 = REG_EMC_SMCR3 = REG_EMC_SMCR4 = 0x6621200; #else REG_EMC_SMCR1 = REG_EMC_SMCR2 = REG_EMC_SMCR3 = REG_EMC_SMCR4 = 0x04444400; @@ -543,13 +543,13 @@ static int jz_nand_init(void) { unsigned char cData[5]; int i; - + jz_nand_enable(); - + for(i=0; i<4; i++) { jz_nand_select(i); - + __nand_cmd(NAND_CMD_READID); __nand_addr(NAND_CMD_READ0); cData[0] = __nand_data8(); @@ -557,17 +557,17 @@ static int jz_nand_init(void) cData[2] = __nand_data8(); cData[3] = __nand_data8(); cData[4] = __nand_data8(); - + jz_nand_deselect(i); - + logf("NAND chip %d: 0x%x 0x%x 0x%x 0x%x 0x%x", i+1, cData[0], cData[1], cData[2], cData[3], cData[4]); - + banks[i] = nand_identify(cData); - + if(banks[i] != NULL) nr_banks++; - + if(i == 0 && banks[i] == NULL) { panicf("Unknown NAND flash chip: 0x%x 0x%x 0x%x 0x%x 0x%x", cData[0], @@ -576,17 +576,17 @@ static int jz_nand_init(void) } } chip_info = banks[0]; - + internal_param.bus_width = 8; internal_param.row_cycle = chip_info->row_cycles; internal_param.page_size = chip_info->page_size; internal_param.oob_size = chip_info->spare_size; internal_param.page_per_block = chip_info->pages_per_block; - + bank_size = chip_info->page_size * chip_info->blocks_per_bank / 512 * chip_info->pages_per_block; - + jz_nand_disable(); - + return 0; } @@ -594,7 +594,7 @@ int nand_init(void) { int res = 0; static bool inited = false; - + if(!inited) { res = jz_nand_init(); @@ -604,7 +604,7 @@ int nand_init(void) semaphore_init(&nand_dma_complete, 1, 0); system_enable_irq(DMA_IRQ(DMA_NAND_CHANNEL)); #endif - + inited = true; } @@ -615,7 +615,7 @@ static inline int read_sector(unsigned long start, unsigned int count, void* buf, unsigned int chip_size) { register int ret; - + if(UNLIKELY(start % chip_size == 0 && count == chip_size)) ret = jz_nand_read_page(start / chip_size, buf); else @@ -623,7 +623,7 @@ static inline int read_sector(unsigned long start, unsigned int count, ret = jz_nand_read_page(start / chip_size, temp_page); memcpy(buf, temp_page + (start % chip_size), count); } - + return ret; } @@ -635,13 +635,13 @@ int nand_read_sectors(IF_MV(int drive,) unsigned long start, int count, void* bu int ret = 0; unsigned int i, _count, chip_size = chip_info->page_size; unsigned long _start; - + logf("start"); mutex_lock(&nand_mtx); - + _start = start << 9; _count = count << 9; - + if(_count <= chip_size) { jz_nand_select(start / bank_size); @@ -653,19 +653,19 @@ int nand_read_sectors(IF_MV(int drive,) unsigned long start, int count, void* bu for(i=0; i<_count && ret==0; i+=chip_size) { jz_nand_select((start+(i>>9)) / bank_size); - + ret = read_sector(_start+i, (_count-i < chip_size ? _count-i : chip_size), buf+i, chip_size); - + jz_nand_deselect((start+(i>>9)) / bank_size); } } - + mutex_unlock(&nand_mtx); - + logf("nand_read_sectors(%ld, %d, 0x%x): %d", start, count, (int)buf, ret); - + return ret; } @@ -732,7 +732,7 @@ void nand_get_info(IF_MV(int drive,) struct storage_info *info) #ifdef HAVE_MULTIVOLUME (void)drive; #endif - + /* firmware version */ info->revision="0.00"; @@ -750,7 +750,7 @@ int nand_num_drives(int first_drive) { /* We don't care which logical drive number(s) we have been assigned */ (void)first_drive; - + return 1; } #endif -- cgit v1.2.3