From adb978a44d39598cb26d2fde5cfe74b2a37a3cda Mon Sep 17 00:00:00 2001 From: Rafaël Carré Date: Wed, 13 May 2009 08:27:20 +0000 Subject: Sansa AMS: Various fixes/enhancements for clock frequencies Fix CGU_DBOP setting Set PCLK to the exact frequency (62MHz, not the maximal frequency) Use a better comment for CLK_DIV macro Use preprocessor safety checks for clock divider sizes to avoid future mistakes (not for SD_IDENT frequency since that check is handled by mci_set_clock_divider) Use maximal IDE frequency of 66MHz (like OF), not 90MHz like written in AS3525 datasheet. The IDE chip is somehow linked to internal storage, and a too high frequency could affect the storage driver. Use the same DBOP frequency of 32MHz for all models (like OF, verified clip, fuze, e200v2 and m200v4), compromise between performance and battery life could be added in the future for each target Performance increase on Sansa Fuze with DBOP freq. set to 64MHz: +12% fps for lcd_update, +1% fps for yuv Thanks to daytona955 on the forums for his help git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20923 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/as3525/clock-target.h | 35 +++++++++++----------- .../target/arm/as3525/sansa-c200v2/lcd-c200v2.c | 2 +- .../target/arm/as3525/sansa-clip/lcd-ssd1303.c | 2 +- .../target/arm/as3525/sansa-e200v2/lcd-e200v2.c | 2 +- firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c | 2 +- 5 files changed, 22 insertions(+), 21 deletions(-) (limited to 'firmware/target/arm') diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index a227f464ff..21fd4c65d2 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h @@ -21,6 +21,9 @@ #ifndef CLOCK_TARGET_H #define CLOCK_TARGET_H +/* returns clock divider, given maximal target frequency and clock reference */ +#define CLK_DIV(ref, target) ((ref + target - 1) / target) + /* PLL */ #define AS3525_PLLA_FREQ 248000000 @@ -39,28 +42,26 @@ /* peripherals */ -#define AS3525_PCLK_FREQ 65000000 - -#define AS3525_IDE_FREQ 90000000 +#define AS3525_PCLK_FREQ 62000000 +#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) >= (1<<4) /* 4 bits */ +#error PCLK frequency is too low : clock divider will not fit ! +#endif -#define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ +#define AS3525_IDE_FREQ 66000000 +#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) >= (1<<4) /* 4 bits */ +#error IDE frequency is too low : clock divider will not fit ! +#endif #define AS3525_I2C_FREQ 400000 +#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_I2C_FREQ)) >= (1<<16) /* 2*8 bits */ +#error I2C frequency is too low : clock divider will not fit ! +#endif -/* LCD controller : varies on the models */ -#if defined(SANSA_CLIP) -#define AS3525_DBOP_FREQ 6000000 -#elif defined(SANSA_M200V4) -#define AS3525_DBOP_FREQ 8000000 -#elif defined(SANSA_FUZE) -#define AS3525_DBOP_FREQ 8000000 -#elif defined(SANSA_E200V2) -#define AS3525_DBOP_FREQ 8000000 -#elif defined(SANSA_C200V2) -#define AS3525_DBOP_FREQ 8000000 +#define AS3525_DBOP_FREQ 32000000 +#if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) >= (1<<3) /* 3 bits */ +#error DBOP frequency is too low : clock divider will not fit ! #endif -/* macro for not giving a target clock > at the one provided */ -#define CLK_DIV(ref, target) ((ref + target - 1) / target) +#define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ #endif /* CLOCK_TARGET_H */ diff --git a/firmware/target/arm/as3525/sansa-c200v2/lcd-c200v2.c b/firmware/target/arm/as3525/sansa-c200v2/lcd-c200v2.c index 88adcd9d96..0ffe0bdc8d 100644 --- a/firmware/target/arm/as3525/sansa-c200v2/lcd-c200v2.c +++ b/firmware/target/arm/as3525/sansa-c200v2/lcd-c200v2.c @@ -98,7 +98,7 @@ static void lcd_delay(int x) /* DBOP initialisation, do what OF does */ static void ams3525_dbop_init(void) { - CGU_DBOP = (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ); + CGU_DBOP = (1<<3) | (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1); DBOP_TIMPOL_01 = 0xe167e167; DBOP_TIMPOL_23 = 0xe167006e; diff --git a/firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c b/firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c index 4669abdf7d..a88e5faa0a 100644 --- a/firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c +++ b/firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c @@ -70,7 +70,7 @@ /* DBOP initialisation, do what OF does */ static void ams3525_dbop_init(void) { - CGU_DBOP |= (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ); + CGU_DBOP |= (1<<3) | (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1); GPIOB_AFSEL = 0x08; /* DBOP on pin 3 */ GPIOC_AFSEL = 0x0f; /* DBOP on pins 3:0 */ diff --git a/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c b/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c index ef21893494..9e23dac340 100644 --- a/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c +++ b/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c @@ -108,7 +108,7 @@ static void lcd_delay(int x) /* DBOP initialisation, do what OF does */ static void ams3525_dbop_init(void) { - CGU_DBOP = (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ); + CGU_DBOP = (1<<3) | (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1); DBOP_TIMPOL_01 = 0xe167e167; DBOP_TIMPOL_23 = 0xe167006e; diff --git a/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c b/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c index 141b890861..f0c85f53b4 100644 --- a/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c +++ b/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c @@ -50,7 +50,7 @@ static bool lcd_busy = false; static void as3525_dbop_init(void) { - CGU_DBOP = (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ); + CGU_DBOP = (1<<3) | (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1); DBOP_TIMPOL_01 = 0xe167e167; DBOP_TIMPOL_23 = 0xe167006e; -- cgit v1.2.3