From 57969698ced265492d2007d39e350b337e163ea4 Mon Sep 17 00:00:00 2001 From: Cástor Muñoz Date: Mon, 10 Nov 2014 02:39:16 +0100 Subject: iPod Classic: update timer API using 32-bit timers. Change-Id: I49dab8ae955a339ad0a27402fa21caa411c4ecf6 Reviewed-on: http://gerrit.rockbox.org/1032 Reviewed-by: Marcin Bukat --- firmware/target/arm/s5l8702/system-s5l8702.c | 27 ++++++++----- firmware/target/arm/s5l8702/timer-s5l8702.c | 57 +++++++++++----------------- 2 files changed, 39 insertions(+), 45 deletions(-) (limited to 'firmware/target/arm') diff --git a/firmware/target/arm/s5l8702/system-s5l8702.c b/firmware/target/arm/s5l8702/system-s5l8702.c index c3f20c506b..09aff3d84e 100644 --- a/firmware/target/arm/s5l8702/system-s5l8702.c +++ b/firmware/target/arm/s5l8702/system-s5l8702.c @@ -39,15 +39,14 @@ default_interrupt(INT_IRQ3); default_interrupt(INT_IRQ4); default_interrupt(INT_IRQ5); default_interrupt(INT_IRQ6); -default_interrupt(INT_IRQ7); -default_interrupt(INT_TIMERA); -default_interrupt(INT_TIMERB); -default_interrupt(INT_TIMERC); -default_interrupt(INT_TIMERD); -default_interrupt(INT_TIMERE); +default_interrupt(INT_TIMERE); /* IRQ7: 32-bit timers */ default_interrupt(INT_TIMERF); default_interrupt(INT_TIMERG); default_interrupt(INT_TIMERH); +default_interrupt(INT_TIMERA); /* IRQ8: 16-bit timers */ +default_interrupt(INT_TIMERB); +default_interrupt(INT_TIMERC); +default_interrupt(INT_TIMERD); default_interrupt(INT_IRQ9); default_interrupt(INT_IRQ10); default_interrupt(INT_IRQ11); @@ -129,9 +128,16 @@ void INT_TIMER() if (TBCON & (TBCON >> 4) & 0x7000) INT_TIMERB(); if (TCCON & (TCCON >> 4) & 0x7000) INT_TIMERC(); if (TDCON & (TDCON >> 4) & 0x7000) INT_TIMERD(); - if (TFCON & (TFCON >> 4) & 0x7000) INT_TIMERF(); - if (TGCON & (TGCON >> 4) & 0x7000) INT_TIMERG(); - if (THCON & (THCON >> 4) & 0x7000) INT_TIMERH(); +} + +void INT_TIMER32(void) ICODE_ATTR; +void INT_TIMER32() +{ + uint32_t tstat = TSTAT; + /*if ((TECON >> 12) & 0x7 & (tstat >> 24)) INT_TIMERE();*/ + if ((TFCON >> 12) & 0x7 & (tstat >> 16)) INT_TIMERF(); + if ((TGCON >> 12) & 0x7 & (tstat >> 8)) INT_TIMERG(); + if ((THCON >> 12) & 0x7 & tstat) INT_TIMERH(); } void INT_DMAC0(void) ICODE_ATTR; @@ -164,7 +170,7 @@ void INT_DMAC1() static void (* const irqvector[])(void) = { - INT_IRQ0,INT_IRQ1,INT_IRQ2,INT_IRQ3,INT_IRQ4,INT_IRQ5,INT_IRQ6,INT_IRQ7, + INT_IRQ0,INT_IRQ1,INT_IRQ2,INT_IRQ3,INT_IRQ4,INT_IRQ5,INT_IRQ6,INT_TIMER32, INT_TIMER,INT_IRQ9,INT_IRQ10,INT_IRQ11,INT_IRQ12,INT_IRQ13,INT_IRQ14,INT_IRQ15, INT_DMAC0,INT_DMAC1,INT_IRQ18,INT_USB_FUNC,INT_IRQ20,INT_IRQ21,INT_IRQ22,INT_WHEEL, INT_IRQ24,INT_IRQ25,INT_IRQ26,INT_IRQ27,INT_IRQ28,INT_ATA,INT_IRQ30,INT_IRQ31, @@ -220,6 +226,7 @@ void system_init(void) VIC0INTENABLE = 1 << IRQ_WHEEL; VIC0INTENABLE = 1 << IRQ_ATA; VIC1INTENABLE = 1 << (IRQ_MMC - 32); + VIC0INTENABLE = 1 << IRQ_TIMER32; } void system_reboot(void) diff --git a/firmware/target/arm/s5l8702/timer-s5l8702.c b/firmware/target/arm/s5l8702/timer-s5l8702.c index 61d4d590e4..7c69ab123a 100644 --- a/firmware/target/arm/s5l8702/timer-s5l8702.c +++ b/firmware/target/arm/s5l8702/timer-s5l8702.c @@ -26,13 +26,11 @@ #include "system.h" #include "timer.h" -//TODO: This needs calibration once we figure out the clocking - -void INT_TIMERC(void) +void INT_TIMERF(void) { /* clear interrupt */ - TCCON = TCCON; - + TSTAT = (0x07 << 16); + if (pfn_timer != NULL) { pfn_timer(); } @@ -40,12 +38,8 @@ void INT_TIMERC(void) bool timer_set(long cycles, bool start) { - static const int cs_table[] = {1, 2, 4, 6}; - int prescale, cs; - long count; - - /* stop and clear timer */ - TCCMD = (1 << 1); /* TD_CLR */ + /* stop timer */ + TFCMD = (0 << 0); /* TF_ENABLE */ /* optionally unregister any previously registered timer user */ if (start) { @@ -55,40 +49,33 @@ bool timer_set(long cycles, bool start) } } - /* scale the count down with the clock select */ - for (cs = 0; cs < 4; cs++) { - count = cycles >> cs_table[cs]; - if ((count < 65536) || (cs == 3)) { - break; - } - } - - /* scale the count down with the prescaler */ - prescale = 1; - while (count >= 65536) { - count >>= 1; - prescale <<= 1; - } + /* There is an odd behaviour when the 32-bit timers are launched + for the first time, the interrupt status bits are set and an + unexpected interrupt is generated if they are enabled. A way to + workaround this is to write the data registers before clearing + the counter. */ + TFDATA0 = cycles; + TFCMD = (1 << 1); /* TF_CLR */ /* configure timer */ - TCCON = (1 << 12) | /* TD_INT0_EN */ - (cs << 8) | /* TS_CS */ - (0 << 4); /* TD_MODE_SEL, 0 = interval mode */ - TCPRE = prescale - 1; - TCDATA0 = count; - TCCMD = (1 << 0); /* TD_ENABLE */ - + TFCON = (1 << 12) | /* TF_INT0_EN */ + (4 << 8) | /* TF_CS, 4 = ECLK / 1 */ + (1 << 6) | /* use ECLK (12MHz) */ + (0 << 4); /* TF_MODE_SEL, 0 = interval mode */ + TFPRE = 0; /* no prescaler */ + + TFCMD = (1 << 0); /* TF_ENABLE */ + return true; } bool timer_start(void) { - TCCMD = (1 << 0); /* TD_ENABLE */ + TFCMD = (1 << 0); /* TF_ENABLE */ return true; } void timer_stop(void) { - TCCMD = (0 << 0); /* TD_ENABLE */ + TFCMD = (0 << 0); /* TF_ENABLE */ } - -- cgit v1.2.3