From a6b31f18c89029c6f19609dc39cbb0abc59daeed Mon Sep 17 00:00:00 2001
From: Maurus Cuelenaere <mcuelenaere@gmail.com>
Date: Sat, 3 May 2008 13:43:26 +0000
Subject: 1) add support for ata-as-arm 2) remove obsolete audio-creativezvm.c
 3) fix registers in i2c-dm320.c

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17316 a1c6a512-1295-4272-9138-f99709370657
---
 .../arm/tms320dm320/creative-zvm/ata-creativezvm.c | 102 ++++++++++++++++++---
 1 file changed, 88 insertions(+), 14 deletions(-)

(limited to 'firmware/target/arm/tms320dm320/creative-zvm/ata-creativezvm.c')

diff --git a/firmware/target/arm/tms320dm320/creative-zvm/ata-creativezvm.c b/firmware/target/arm/tms320dm320/creative-zvm/ata-creativezvm.c
index 331803360f..252239b62b 100644
--- a/firmware/target/arm/tms320dm320/creative-zvm/ata-creativezvm.c
+++ b/firmware/target/arm/tms320dm320/creative-zvm/ata-creativezvm.c
@@ -25,11 +25,18 @@
 #include "power.h"
 #include "panic.h"
 #include "ata-target.h"
+#include "dm320.h"
+
+void sleep_ms(int ms)
+{
+    sleep(ms*HZ/1000);
+}
 
 void ide_power_enable(bool on)
 {
+/* Disabled until figured out what's wrong */
 #if 0
-    IO_INTC_EINT1 &= ~INTR_EINT1_EXT2;
+    int old_level = disable_irq_save();
     if(on)
     {
         IO_GIO_BITSET0 = (1 << 14);
@@ -37,8 +44,7 @@ void ide_power_enable(bool on)
     }
     else
         IO_GIO_BITCLR0 = (1 << 14);
-    IO_INTC_EINT1 |= INTR_EINT1_EXT2;
-    return;
+    restore_irq(old_level);
 #else
     (void)on;
 #endif
@@ -55,26 +61,24 @@ inline bool ide_powered()
 
 void ata_reset(void)
 {
-/* Disabled until figured out what's wrong */
-    IO_INTC_EINT1 &= ~INTR_EINT1_EXT2; /*disable GIO2 interrupt */
+    int old_level = disable_irq_save();
     if(!ide_powered())
     {
         ide_power_enable(true);
-        sleep(150);
+        sleep_ms(150);
     }
     else
     {
         IO_GIO_BITSET0 = (1 << 5);
         IO_GIO_BITCLR0 = (1 << 3);
-        sleep(1);
+        sleep_ms(1);
     }
     IO_GIO_BITCLR0 = (1 << 5);
-    sleep(10);
+    sleep_ms(10);
     IO_GIO_BITSET0 = (1 << 3);
     while(!(ATA_COMMAND & STATUS_RDY))
-        sleep(10);
-    IO_INTC_EINT1 |= INTR_EINT1_EXT2; //enable GIO2 interrupt
-    return;
+        sleep_ms(10);
+    restore_irq(old_level);
 }
 
 void ata_enable(bool on)
@@ -88,9 +92,79 @@ bool ata_is_coldstart(void)
     return true;
 }
 
+#if 0 /* Disabled as device crashes; probably due to SDRAM addresses aren't 32-bit aligned */
+#define CS1_START       0x50000000
+#define DEST_ADDR       (ATA_IOBASE-CS1_START)
+static struct wakeup transfer_completion_signal;
+
+void MTC0(void)
+{
+    IO_INTC_IRQ1 = 1 << IRQ_MTC0;
+    wakeup_signal(&transfer_completion_signal);
+}
+
+void copy_read_sectors(unsigned char* buf, int wordcount)
+{
+    bool lasthalfword = false;
+    unsigned short tmp;
+    if(wordcount < 16)
+    {
+        _copy_read_sectors(buf, wordcount);
+        return;
+    }
+    else if((unsigned long)buf % 32) /* Not 32-byte aligned */
+    {
+        unsigned char* bufend = buf + ((unsigned long)buf % 32);
+        if( ((unsigned long)buf % 32) % 2 )
+            lasthalfword = true;
+        wordcount -= ((unsigned long)buf % 32) / 2;
+        do
+        {
+            tmp = ATA_DATA;
+            *buf++ = tmp >> 8;
+            *buf++ = tmp & 0xff;
+        } while (buf < bufend); /* tail loop is faster */
+    }
+    IO_SDRAM_SDDMASEL = 0x0830; /* 32-byte burst mode transfer */
+    IO_EMIF_AHBADDH = ((unsigned)buf >> 16) & ~(1 << 15); /* Set variable address */
+    IO_EMIF_AHBADDL = (unsigned)buf & 0xFFFF;
+    IO_EMIF_DMAMTCSEL = 1; /* Select CS1 */
+    IO_EMIF_MTCADDH = ( (1 << 15) | (DEST_ADDR >> 16) ); /* Set fixed address */
+    IO_EMIF_MTCADDL = DEST_ADDR & 0xFFFF;
+    IO_EMIF_DMASIZE = wordcount*2;
+    IO_EMIF_DMACTL = 3; /* Select MTC->AHB and start transfer */
+    //wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
+    while(IO_EMIF_DMACTL & 1)
+        nop;
+    if(lasthalfword)
+    {
+        *buf += wordcount * 2;
+        tmp = ATA_DATA;
+        *buf++ = tmp >> 8;
+        *buf++ = tmp & 0xff;
+    }
+}
+void copy_write_sectors(const unsigned char* buf, int wordcount)
+{
+    IO_EMIF_DMAMTCSEL = 1; /* Select CS1 */
+    IO_SDRAM_SDDMASEL = 0x0820; /* Temporarily set to standard value */
+    IO_EMIF_AHBADDH = ((int)buf >> 16) & ~(1 << 15); /* Set variable address */
+    IO_EMIF_AHBADDL = (int)buf & 0xFFFF;
+    IO_EMIF_MTCADDH = ( (1 << 15) | (DEST_ADDR >> 16) ); /* Set fixed address */
+    IO_EMIF_MTCADDL = DEST_ADDR & 0xFFFF;
+    IO_EMIF_DMASIZE = wordcount;
+    IO_EMIF_DMACTL = 1; /* Select AHB->MTC and start transfer */
+    wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
+}
+#endif
+
 void ata_device_init(void)
 {
-    IO_INTC_EINT1 |= INTR_EINT1_EXT2;   //enable GIO2 interrupt
+    IO_INTC_EINT1 |= INTR_EINT1_EXT2;   /* enable GIO2 interrupt */
+#if 0
+    IO_INTC_EINT1 |= 1 << IRQ_MTC0;     /* enable MTC interrupt */
+    wakeup_init(&transfer_completion_signal);
+#endif
     //TODO: mimic OF inits...
     return;
 }
@@ -98,8 +172,8 @@ void ata_device_init(void)
 void GIO2(void)
 {
 #ifdef DEBUG
-    //printf("GIO2 interrupt...");
+    logf("GIO2 interrupt...");
 #endif
-    IO_INTC_IRQ1 = INTR_IRQ1_EXT2; //Mask GIO2 interrupt
+    IO_INTC_IRQ1 = INTR_IRQ1_EXT2; /* Mask GIO2 interrupt */
     return;
 }
-- 
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