From 6a67707b5ec3b2c649c401550bb7fdef2b7c8d07 Mon Sep 17 00:00:00 2001 From: Michael Sevakis Date: Sat, 17 Dec 2011 07:27:24 +0000 Subject: Commit to certain names for cache coherency APIs and discard the aliases. Wouldn't surprise me a bit to get some non-green. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31339 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/thread-pp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'firmware/target/arm/thread-pp.c') diff --git a/firmware/target/arm/thread-pp.c b/firmware/target/arm/thread-pp.c index a0a4d4fd17..0836b27204 100644 --- a/firmware/target/arm/thread-pp.c +++ b/firmware/target/arm/thread-pp.c @@ -214,7 +214,7 @@ static inline void NORETURN_ATTR __attribute__((always_inline)) { asm volatile ( "cmp %1, #0 \n" /* CPU? */ - "ldrne r0, =cpucache_flush \n" /* No? write back data */ + "ldrne r0, =commit_dcache \n" /* No? write back data */ "movne lr, pc \n" "bxne r0 \n" "mov r0, %0 \n" /* copy thread parameter */ @@ -244,7 +244,7 @@ static inline void NORETURN_ATTR __attribute__((always_inline)) static void core_switch_blk_op(unsigned int core, struct thread_entry *thread) { /* Flush our data to ram */ - cpucache_flush(); + commit_dcache(); /* Stash thread in r4 slot */ thread->context.r[0] = (uint32_t)thread; /* Stash restart address in r5 slot */ @@ -285,7 +285,7 @@ static void __attribute__((naked)) "ldr sp, [r0, #32] \n" /* Reload original sp from context structure */ "mov r1, #0 \n" /* Clear start address */ "str r1, [r0, #40] \n" - "ldr r0, =cpucache_invalidate \n" /* Invalidate new core's cache */ + "ldr r0, =commit_discard_idcache \n" /* Invalidate new core's cache */ "mov lr, pc \n" "bx r0 \n" "ldmfd sp!, { r4-r11, pc } \n" /* Restore non-volatile context to new core and return */ -- cgit v1.2.3