From a50a80e1a3bcff9e3c739d796605c10e1f8e8d05 Mon Sep 17 00:00:00 2001 From: Jens Arnold Date: Thu, 8 Nov 2007 06:52:48 +0000 Subject: Mini 2nd Gen: Almost doubled LCD update speed when not boosted (68.5->129fps @30MHz) by handling the serial LCD clock divider. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15524 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/system-pp502x.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'firmware/target/arm/system-pp502x.c') diff --git a/firmware/target/arm/system-pp502x.c b/firmware/target/arm/system-pp502x.c index 0f24997451..a1c4d1639e 100644 --- a/firmware/target/arm/system-pp502x.c +++ b/firmware/target/arm/system-pp502x.c @@ -178,6 +178,9 @@ static void pp_set_cpu_frequency(long frequency) case CPUFREQ_MAX: CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ DEV_TIMING1 = 0x00000303; +#ifdef IPOD_MINI2G + MLCD_SCLK_DIV = 0x00000001; /* Mono LCD bridge serial clock divider */ +#endif #if CONFIG_CPU == PP5020 PLL_CONTROL = 0x8a020a03; /* 10/3 * 24MHz */ PLL_STATUS = 0xd19b; /* unlock frequencies > 66MHz */ @@ -196,6 +199,9 @@ static void pp_set_cpu_frequency(long frequency) case CPUFREQ_NORMAL: CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ DEV_TIMING1 = 0x00000303; +#ifdef IPOD_MINI2G + MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */ +#endif #if CONFIG_CPU == PP5020 PLL_CONTROL = 0x8a020504; /* 5/4 * 24MHz */ scale_suspend_core(false); @@ -220,6 +226,9 @@ static void pp_set_cpu_frequency(long frequency) default: CLOCK_SOURCE = 0x10002222; /* source #1, #2, #3, #4: 24MHz */ DEV_TIMING1 = 0x00000303; +#ifdef IPOD_MINI2G + MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */ +#endif PLL_CONTROL &= ~0x80000000; /* disable PLL */ cpu_frequency = CPUFREQ_DEFAULT; PROC_CTL(CURRENT_CORE) = 0x4800001f; nop; -- cgit v1.2.3