From 05099149f193cac0c81b0129c17feb78b1a9681a Mon Sep 17 00:00:00 2001 From: Michael Sevakis Date: Sun, 6 Apr 2008 04:34:57 +0000 Subject: Enable nocache sections using the linker. PP5022/4 must use SW_CORELOCK now with shared variables in DRAM (it seems swp(b) is at least partially broken on all PP or I'm doing something very wrong here :\). For core-shared data use SHAREDBSS/DATA_ATTR. NOCACHEBSS/DATA_ATTR is available whether or not single core is forced for static peripheral-DMA buffer allocation without use of the UNCACHED_ADDR macro in code and is likely useful on a non-PP target with a data cache (although not actually enabled in config.h and the .lds's in this commit). git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16981 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/sandisk/sansa-e200/lcd-e200.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'firmware/target/arm/sandisk/sansa-e200/lcd-e200.c') diff --git a/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c b/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c index f2689eabbf..15263b5533 100644 --- a/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c +++ b/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c @@ -28,8 +28,8 @@ /* Power and display status */ static bool power_on = false; /* Is the power turned on? */ -static bool display_on NOCACHEBSS_ATTR = false; /* Is the display turned on? */ -static unsigned lcd_yuv_options NOCACHEBSS_ATTR = 0; +static bool display_on SHAREDBSS_ATTR = false; /* Is the display turned on? */ +static unsigned lcd_yuv_options SHAREDBSS_ATTR = 0; /* Reverse Flag */ #define R_DISP_CONTROL_NORMAL 0x0004 -- cgit v1.2.3