From 758bb3bc628705ff8e5c677b3b2d87720c726c13 Mon Sep 17 00:00:00 2001
From: Mark Arigo <markarigo@gmail.com>
Date: Mon, 25 May 2009 21:10:45 +0000
Subject: 3 new ports: Samsung YH-820, YH-920, and YH-925. Mostly functional.
 Audio working on 820 & 925 (untested on the 920). No battery readings. No
 recording. No plugins. Keymap needs work.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21083 a1c6a512-1295-4272-9138-f99709370657
---
 firmware/target/arm/samsung/app.lds | 198 ++++++++++++++++++++++++++++++++++++
 1 file changed, 198 insertions(+)
 create mode 100644 firmware/target/arm/samsung/app.lds

(limited to 'firmware/target/arm/samsung/app.lds')

diff --git a/firmware/target/arm/samsung/app.lds b/firmware/target/arm/samsung/app.lds
new file mode 100644
index 0000000000..22468192eb
--- /dev/null
+++ b/firmware/target/arm/samsung/app.lds
@@ -0,0 +1,198 @@
+#include "config.h"
+
+ENTRY(start)
+
+OUTPUT_FORMAT(elf32-littlearm)
+OUTPUT_ARCH(arm)
+STARTUP(target/arm/crt0-pp.o)
+
+#define PLUGINSIZE PLUGIN_BUFFER_SIZE
+#define CODECSIZE CODEC_SIZE
+
+#ifdef DEBUG
+#define STUBOFFSET 0x10000
+#else
+#define STUBOFFSET 0
+#endif
+
+#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - STUBOFFSET - CODECSIZE
+
+#define DRAMORIG 0x00000000 + STUBOFFSET
+#define IRAMORIG 0x40000000
+#define IRAMSIZE 0xc000
+
+#ifdef CPU_PP502x
+#define NOCACHE_BASE 	0x10000000
+#else
+#define NOCACHE_BASE 	0x28000000
+#endif
+
+#define CACHEALIGN_SIZE 16
+
+/* End of the audio buffer, where the codec buffer starts */
+#define ENDAUDIOADDR  (DRAMORIG + DRAMSIZE)
+
+/* Where the codec buffer ends, and the plugin buffer starts */
+#define ENDADDR (ENDAUDIOADDR + CODECSIZE)
+
+MEMORY
+{
+    DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
+    IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
+}
+
+SECTIONS
+{
+    .text :
+    {
+        loadaddress = .;
+        _loadaddress = .;
+        . = ALIGN(0x200);
+        *(.init.text)
+        *(.text*)
+        *(.glue_7)
+        *(.glue_7t)
+        . = ALIGN(0x4);
+    } > DRAM
+
+    .rodata :
+    {
+        *(.rodata)  /* problems without this, dunno why */
+        *(.rodata*)
+        *(.rodata.str1.1)
+        *(.rodata.str1.4)
+        . = ALIGN(0x4);
+
+        /* Pseudo-allocate the copies of the data sections */
+        _datacopy = .;
+    } > DRAM
+
+    /* TRICK ALERT! For RAM execution, we put the .data section at the
+       same load address as the copy. Thus, we don't waste extra RAM
+       when we don't actually need the copy.  */
+    .data : AT ( _datacopy )
+    {
+        _datastart = .;
+        *(.data*)
+        . = ALIGN(0x4);
+        _dataend  = .;
+    } > DRAM
+
+#if NOCACHE_BASE != 0
+    /* .ncdata section is placed at uncached physical alias address and is
+     * loaded at the proper cached virtual address - no copying is
+     * performed in the init code */
+    .ncdata . + NOCACHE_BASE :
+    {
+        . = ALIGN(CACHEALIGN_SIZE);
+        *(.ncdata*)
+        . = ALIGN(CACHEALIGN_SIZE);
+    } AT> DRAM
+#endif
+    
+    /DISCARD/ :
+    {
+        *(.eh_frame)
+    }
+
+    .vectors 0x0 :
+    {
+        _vectorsstart = .;
+        *(.vectors);
+        _vectorsend = .;
+    } AT> DRAM
+
+    _vectorscopy = LOADADDR(.vectors);
+    _noloaddram  = LOADADDR(.vectors);
+
+    .ibss IRAMORIG (NOLOAD) :
+    {
+        _iedata = .;
+        *(.qharray)
+        *(.ibss)
+        . = ALIGN(0x4);
+        _iend = .;
+    } > IRAM
+
+    .iram _iend :
+    {
+        _iramstart = .;
+        *(.icode)
+        *(.irodata)
+        *(.idata)
+        . = ALIGN(0x4);
+        _iramend = .;
+    } > IRAM AT> DRAM
+
+    _iramcopy = LOADADDR(.iram);
+
+    .idle_stacks (NOLOAD) :
+    {
+       *(.idle_stacks)
+#if NUM_CORES > 1
+       cpu_idlestackbegin = .;
+       . += IDLE_STACK_SIZE;
+       cpu_idlestackend = .;
+#endif
+       cop_idlestackbegin = .;
+       . += IDLE_STACK_SIZE;
+       cop_idlestackend = .;
+    } > IRAM
+
+    .stack (NOLOAD) :
+    {
+       *(.stack)
+       stackbegin = .;
+       . += 0x2000;
+       stackend = .;
+    } > IRAM
+
+    /* .bss and .ncbss are treated as a single section to use one init loop to
+     * zero it - note "_edata" and "_end" */
+    .bss _noloaddram (NOLOAD) :
+    {
+       _edata = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(0x4);
+    } > DRAM
+
+#if NOCACHE_BASE != 0
+    .ncbss . + NOCACHE_BASE (NOLOAD):
+    {
+    	. = ALIGN(CACHEALIGN_SIZE);
+        *(.ncbss*)
+    	. = ALIGN(CACHEALIGN_SIZE);
+    } AT> DRAM
+#endif
+
+    /* This will be aligned by preceding alignments */
+    .endaddr . - NOCACHE_BASE (NOLOAD) :
+    {
+        _end = .;
+    } > DRAM
+
+    .audiobuf (NOLOAD) :
+    {
+        _audiobuffer = .;
+        audiobuffer = .;
+    } > DRAM
+    
+    .audiobufend ENDAUDIOADDR (NOLOAD) :
+    {
+        audiobufend = .;
+        _audiobufend = .;
+    } > DRAM
+
+    .codec ENDAUDIOADDR (NOLOAD) :
+    {
+        codecbuf = .;
+        _codecbuf = .;
+    }
+
+    .plugin ENDADDR (NOLOAD) :
+    {
+        _pluginbuf = .;
+        pluginbuf = .;
+    }
+}
-- 
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