From 9f27dc210337e015113776dd5a24b96aabefd70c Mon Sep 17 00:00:00 2001 From: Cástor Muñoz Date: Sat, 6 Dec 2014 21:19:02 +0100 Subject: iPod Classic: introduce s5l8702 UART driver - polling/IRQ modes for Tx/Rx (TODO?: DMA) - fine adjust for Tx/Rx bitrates - auto bauding using HW circuitry - status and stats in debug screen Change-Id: I8650957063bc6d274d92eba2779d93ae73453fb6 --- firmware/target/arm/s5l8702/uc8702.c | 446 +++++++++++++++++++++++++++++++++++ firmware/target/arm/s5l8702/uc8702.h | 321 +++++++++++++++++++++++++ 2 files changed, 767 insertions(+) create mode 100644 firmware/target/arm/s5l8702/uc8702.c create mode 100644 firmware/target/arm/s5l8702/uc8702.h (limited to 'firmware/target/arm/s5l8702') diff --git a/firmware/target/arm/s5l8702/uc8702.c b/firmware/target/arm/s5l8702/uc8702.c new file mode 100644 index 0000000000..91c4a3c9e6 --- /dev/null +++ b/firmware/target/arm/s5l8702/uc8702.c @@ -0,0 +1,446 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2014 by Cástor Muñoz + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#include +#include "kernel.h" +#include "uc8702.h" + + +/* + * s5l8702 UART controller (UC8702) + */ + +/* Rx related masks */ +#define UTRSTAT_RX_RELATED_INTS \ + (UTRSTAT_RX_INT_BIT | UTRSTAT_RX_TOUT_INT_BIT | \ + UTRSTAT_ERR_INT_BIT | UTRSTAT_AUTOBR_INT_BIT) +#define UCON_RX_RELATED_INTS \ + (UCON_RX_INT_BIT | UCON_RX_TOUT_INT_BIT | \ + UCON_ERR_INT_BIT | UCON_AUTOBR_INT_BIT) + +/* Initialization */ +static void uartc_port_id_reset(struct uartc* uartc, int id) +{ + uint32_t baddr = UART_PORT_BASE(uartc->baddr, id); + + /* set port registers to default reset values */ + UCON(baddr) = 0; + ULCON(baddr) = 0; + UMCON(baddr) = 0; + UFCON(baddr) = UFCON_RX_FIFO_RST_BIT | UFCON_TX_FIFO_RST_BIT; + /* clear all interrupts */ + UTRSTAT(baddr) = UTRSTAT_RX_RELATED_INTS + | UTRSTAT_TX_INT_BIT + | UTRSTAT_MODEM_INT_BIT; + UBRDIV(baddr) = 0; + UBRCONTX(baddr) = 0; + UBRCONRX(baddr) = 0; + + uartc->port_l[id] = (void*)0; +} + +static void uartc_reset(struct uartc* uartc) +{ + for (int id = 0; id < UART_PORT_MAX; id++) + uartc_port_id_reset(uartc, id); +} + +void uartc_open(struct uartc* uartc) + __attribute__((alias("uartc_reset"))); + +void uartc_close(struct uartc* uartc) + __attribute__((alias("uartc_reset"))); + +void uartc_port_open(struct uartc_port *port) +{ + struct uartc *uartc = port->uartc; + uint32_t baddr = UART_PORT_BASE(uartc->baddr, port->id); + + port->baddr = baddr; + port->utrstat_int_mask = (port->rx_cb ? UTRSTAT_RX_RELATED_INTS : 0) + | (port->tx_cb ? UTRSTAT_TX_INT_BIT : 0); + port->abr_aborted = 0; + + /* disable Tx/Rx and mask all interrupts */ + UCON(baddr) = 0; + + /* clear all interrupts */ + UTRSTAT(baddr) = UTRSTAT_RX_RELATED_INTS + | UTRSTAT_TX_INT_BIT + | UTRSTAT_MODEM_INT_BIT; + + /* configure registers */ + UFCON(baddr) = UFCON_FIFO_ENABLE_BIT + | UFCON_RX_FIFO_RST_BIT + | UFCON_TX_FIFO_RST_BIT + | ((port->rx_trg & UFCON_RX_FIFO_TRG_MASK) << UFCON_RX_FIFO_TRG_POS) + | ((port->tx_trg & UFCON_TX_FIFO_TRG_MASK) << UFCON_TX_FIFO_TRG_POS); + + UMCON(baddr) = UMCON_RTS_BIT; /* activate nRTS (low level) */ + + UCON(baddr) = (UCON_MODE_DISABLED << UCON_RX_MODE_POS) + | (UCON_MODE_DISABLED << UCON_TX_MODE_POS) + | ((port->clksel & UCON_CLKSEL_MASK) << UCON_CLKSEL_POS) + | (port->rx_cb ? UCON_RX_RELATED_INTS|UCON_RX_TOUT_EN_BIT : 0) + | (port->tx_cb ? UCON_TX_INT_BIT : 0); + + /* register port on parent controller */ + uartc->port_l[port->id] = port; +} + +void uartc_port_close(struct uartc_port *port) +{ + uartc_port_id_reset(port->uartc, port->id); +} + +/* Configuration */ +void uartc_port_config(struct uartc_port *port, unsigned int speed, + uint8_t data_bits, uint8_t parity, uint8_t stop_bits) +{ + uint32_t baddr = port->baddr; + + ULCON(baddr) = ((parity & ULCON_PARITY_MASK) << ULCON_PARITY_POS) + | ((stop_bits & ULCON_STOP_BITS_MASK) << ULCON_STOP_BITS_POS) + | ((data_bits & ULCON_DATA_BITS_MASK) << ULCON_DATA_BITS_POS); + + uartc_port_set_bitrate(port, speed); +} + +void uartc_port_set_bitrate(struct uartc_port *port, unsigned int speed) +{ + uint32_t baddr = port->baddr; + int uclk = port->clkhz; + + /* Real baud width in UCLK/16 ticks: trunc(UCLK/(16*speed) + 0.5) */ + int brdiv = (uclk + (speed << 3)) / (speed << 4); + + UBRDIV(baddr) = brdiv - 1; + + /* Fine adjust: + * + * Along the whole frame, insert/remove "jittered" bauds when needed + * to minimize frame lenght accumulated error. + * + * jitter_width: "jittered" bauds are 1/16 wider/narrower than normal + * bauds, so step is 1/16 of real baud width = brdiv (in UCLK ticks) + * + * baud_err_width: it is the difference between theoric width and real + * width = CLK/speed - brdiv*16 (in UCLK ticks) + * + * Previous widths are scaled by 'speed' factor to simplify operations + * and preserve precision using integer operations. + */ + int jitter_width = brdiv * speed; + int baud_err_width = uclk - (jitter_width << 4); + + int jitter_incdec = UBRCON_JITTER_INC; + if (baud_err_width < 0) { + baud_err_width = -baud_err_width; + jitter_incdec = UBRCON_JITTER_DEC; + } + + int err_width = 0; + uint32_t brcon = 0; + /* TODO: for (bit < configured frame length) */ + for (int bit = 0; bit < UC_FRAME_MAX_LEN; bit++) { + err_width += baud_err_width; + /* adjust to the nearest width */ + if (jitter_width < (err_width << 1)) { + brcon |= jitter_incdec << UBRCON_JITTER_POS(bit); + err_width -= jitter_width; + } + } + + UBRCONRX(baddr) = brcon; + UBRCONTX(baddr) = brcon; +} + +/* TODO: uarc_port_set_bitrate_raw() using precalculated values */ + +/* Select Tx/Rx modes: disabling Tx/Rx resets HW, including + FIFOs and shift registers */ +void uartc_port_set_rx_mode(struct uartc_port *port, uint32_t mode) +{ + UCON(port->baddr) = (mode << UCON_RX_MODE_POS) | + (UCON(port->baddr) & ~(UCON_RX_MODE_MASK << UCON_RX_MODE_POS)); +} + +void uartc_port_set_tx_mode(struct uartc_port *port, uint32_t mode) +{ + UCON(port->baddr) = (mode << UCON_TX_MODE_POS) | + (UCON(port->baddr) & ~(UCON_TX_MODE_MASK << UCON_TX_MODE_POS)); +} + +/* Transmit */ +bool uartc_port_tx_ready(struct uartc_port *port) +{ + return (UTRSTAT(port->baddr) & UTRSTAT_TXBUF_EMPTY_BIT); +} + +void uartc_port_tx_byte(struct uartc_port *port, uint8_t ch) +{ + UTXH(port->baddr) = ch; +#ifdef UC8702_DEBUG + port->n_tx_bytes++; +#endif +} + +void uartc_port_send_byte(struct uartc_port *port, uint8_t ch) +{ + /* wait for transmit buffer empty */ + while (!uartc_port_tx_ready(port)); + uartc_port_tx_byte(port, ch); +} + +/* Receive */ +bool uartc_port_rx_ready(struct uartc_port *port) +{ + /* test receive buffer data ready */ + return (UTRSTAT(port->baddr) & UTRSTAT_RXBUF_RDY_BIT); +} + +uint8_t uartc_port_rx_byte(struct uartc_port *port) +{ + return URXH(port->baddr) & 0xff; +} + +uint8_t uartc_port_read_byte(struct uartc_port *port) +{ + while (!uartc_port_rx_ready(port)); + return uartc_port_rx_byte(port); +} + +/* Autobauding */ +static inline int uartc_port_abr_status(struct uartc_port *port) +{ + return UABRSTAT(port->baddr) & UABRSTAT_STATUS_MASK; +} + +void uartc_port_abr_start(struct uartc_port *port) +{ + port->abr_aborted = 0; + UCON(port->baddr) |= UCON_AUTOBR_START_BIT; +} + +void uartc_port_abr_stop(struct uartc_port *port) +{ + if (uartc_port_abr_status(port) == UABRSTAT_STATUS_COUNTING) + /* There is no known way to stop the HW once COUNTING is + * in progress. + * If we disable AUTOBR_START_BIT now, COUNTING is not + * aborted, instead the HW will launch interrupts for + * every new rising edge detected while AUTOBR_START_BIT + * remains disabled. + * If AUTOBR_START_BIT is enabled, the HW will stop by + * itself when a rising edge is detected. + * So, do not disable AUTOBR_START_BIT and wait for the + * next rising edge. + */ + port->abr_aborted = 1; + else + UCON(port->baddr) &= ~UCON_AUTOBR_START_BIT; +} + +/* ISR */ +void ICODE_ATTR uartc_callback(struct uartc *uartc, int id) +{ + struct uartc_port *port = uartc->port_l[id]; + uint32_t baddr = port->baddr; + + /* filter registered interrupts */ + uint32_t ints = UTRSTAT(baddr) & port->utrstat_int_mask; + + /* clear interrupts, events ocurring while processing + this ISR will be processed in the next call */ + UTRSTAT(baddr) = ints; + + if (ints & UTRSTAT_RX_RELATED_INTS) + { + int len = 0; + uint32_t abr_cnt = 0; + + if (ints & UTRSTAT_AUTOBR_INT_BIT) + { + if (uartc_port_abr_status(port) == UABRSTAT_STATUS_COUNTING) { + #ifdef UC8702_DEBUG + if (UCON(baddr) & UCON_AUTOBR_START_BIT) port->n_abnormal0++; + else port->n_abnormal1++; + #endif + /* try to fix abnormal situations */ + UCON(baddr) |= UCON_AUTOBR_START_BIT; + } + else if (!port->abr_aborted) + abr_cnt = UABRCNT(baddr); + } + + if (ints & (UTRSTAT_RX_RELATED_INTS ^ UTRSTAT_AUTOBR_INT_BIT)) + { + /* get FIFO count */ + uint32_t ufstat = UFSTAT(baddr); + len = (ufstat & UFSTAT_RX_FIFO_CNT_MASK) | + ((ufstat & UFSTAT_RX_FIFO_FULL_BIT) >> (8 - 4)); + + for (int i = 0; i < len; i++) { + /* must read error status first, then data */ + port->rx_err[i] = UERSTAT(baddr); + port->rx_data[i] = URXH(baddr); + } + } + + /* 'abr_cnt' is zero when no ABR interrupt exists, 'len' + * might be zero due to RX_TOUT interrupts are raised by + * the hardware even when RX FIFO is empty. + * When overrun, it is marked on the first readed error: + * overrun = len ? (rx_err[0] & UERSTAT_OVERRUN_BIT) : 0 + */ + port->rx_cb(len, port->rx_data, port->rx_err, abr_cnt); + + #ifdef UC8702_DEBUG + if (len) { + port->n_rx_bytes += len; + if (port->rx_err[0] & UERSTAT_OVERRUN_BIT) + port->n_ovr_err++; + for (int i = 0; i < len; i++) { + if (port->rx_err[i] & UERSTAT_PARITY_ERR_BIT) + port->n_parity_err++; + if (port->rx_err[i] & UERSTAT_FRAME_ERR_BIT) + port->n_frame_err++; + if (port->rx_err[i] & UERSTAT_BREAK_DETECT_BIT) + port->n_break_detect++; + } + } + #endif + } + + #if 0 + /* not used and not tested */ + if (ints & UTRSTAT_TX_INT_BIT) + { + port->tx_cb(UART_FIFO_SIZE - ((UFSTAT(baddr) & \ + UFSTAT_TX_FIFO_CNT_MASK) >> UFSTAT_TX_FIFO_CNT_POS)); + } + #endif +} + + +#ifdef UC8702_DEBUG +/*#define LOGF_ENABLE*/ +#include "logf.h" + +static int get_bitrate(int uclk, int brdiv, int brcon, int frame_len) +{ + logf("get_bitrate(%d, %d, 0x%08x, %d)", uclk, brdiv, brcon, frame_len); + + int avg_speed; + int speed_sum = 0; + unsigned int frame_width = 0; /* in UCLK clock ticks */ + + /* calculate resulting speed for every frame len */ + for (int bit = 0; bit < frame_len; bit++) + { + frame_width += brdiv * 16; + + int incdec = ((brcon >> UBRCON_JITTER_POS(bit)) & UBRCON_JITTER_MASK); + if (incdec == UBRCON_JITTER_INC) frame_width += brdiv; + else if (incdec == UBRCON_JITTER_DEC) frame_width -= brdiv; + + /* speed = truncate((UCLK / (real_frame_width / NBITS)) + 0.5) + XXX: overflows for big UCLK */ + int speed = (((uclk*(bit+1))<<1) + frame_width) / (frame_width<<1); + speed_sum += speed; + logf(" %d: %c %d", bit, ((incdec == UBRCON_JITTER_INC) ? 'i' : + ((incdec == UBRCON_JITTER_DEC) ? 'd' : '.')), speed); + } + + /* average of the speed for all frame lengths */ + avg_speed = speed_sum / frame_len; + logf(" avg speed = %d", avg_speed); + + return avg_speed; +} + +void uartc_port_get_line_info(struct uartc_port *port, + int *tx_status, int *rx_status, + int *tx_speed, int *rx_speed, char *line_cfg) +{ + uint32_t baddr = port->baddr; + + uint32_t ucon = UCON(baddr); + if (*tx_status) + *tx_status = ((ucon >> UCON_TX_MODE_POS) & UCON_TX_MODE_MASK) ? 1 : 0; + if (*rx_status) + *rx_status = ((ucon >> UCON_RX_MODE_POS) & UCON_RX_MODE_MASK) ? 1 : 0; + + uint32_t ulcon = ULCON(baddr); + int n_data = ((ulcon >> ULCON_DATA_BITS_POS) & ULCON_DATA_BITS_MASK) + 5; + int n_stop = ((ulcon >> ULCON_STOP_BITS_POS) & ULCON_STOP_BITS_MASK) + 1; + int parity = (ulcon >> ULCON_PARITY_POS) & ULCON_PARITY_MASK; + int frame_len = 1 + n_data + (parity ? 1 : 0) + n_stop; + + uint32_t brdiv = UBRDIV(baddr) + 1; + if (*tx_speed) + *tx_speed = get_bitrate(port->clkhz, brdiv, UBRCONTX(baddr), frame_len); + if (*rx_speed) + *rx_speed = get_bitrate(port->clkhz, brdiv, UBRCONRX(baddr), frame_len); + + if (*line_cfg) { + line_cfg[0] = '0' + n_data; + line_cfg[1] = ((parity == ULCON_PARITY_NONE) ? 'N' : + ((parity == ULCON_PARITY_EVEN) ? 'E' : + ((parity == ULCON_PARITY_ODD) ? 'O' : + ((parity == ULCON_PARITY_FORCE_1) ? 'M' : + ((parity == ULCON_PARITY_FORCE_0) ? 'S' : '?'))))); + line_cfg[2] = '0' + n_stop; + line_cfg[3] = '\0'; + } +} + +/* Autobauding */ +int uartc_port_get_abr_info(struct uartc_port *port, unsigned int *abr_cnt) +{ + int status; + uint32_t abr_status; + uint32_t baddr = port->baddr; + + int flags = disable_irq_save(); + + abr_status = uartc_port_abr_status(port); + + if (UCON(port->baddr) & UCON_AUTOBR_START_BIT) { + if (abr_status == UABRSTAT_STATUS_COUNTING) + status = ABR_INFO_ST_COUNTING; /* waiting for rising edge */ + else + status = ABR_INFO_ST_LAUNCHED; /* waiting for falling edge */ + } + else { + if (abr_status == UABRSTAT_STATUS_COUNTING) + status = ABR_INFO_ST_ABNORMAL; + else + status = ABR_INFO_ST_IDLE; + } + + if (*abr_cnt) + *abr_cnt = UABRCNT(baddr); + + restore_irq(flags); + + return status; +} +#endif /* UC8702_DEBUG */ diff --git a/firmware/target/arm/s5l8702/uc8702.h b/firmware/target/arm/s5l8702/uc8702.h new file mode 100644 index 0000000000..36e4f8faa4 --- /dev/null +++ b/firmware/target/arm/s5l8702/uc8702.h @@ -0,0 +1,321 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2014 by Cástor Muñoz + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __UC8702_H__ +#define __UC8702_H__ + +#include +#include + + +/* s5l8702 UART controller (UC8702): + * + * This UART is similar to the UART included in s5l8700 (see also + * s3c2416 and s3c6400 datasheets), UC8702 adds fine tunning for + * Tx/Rx bitrate and autobauding. + */ + +/*#define UC8702_DEBUG*/ + +/* + * uc8702 HW definitions + */ +#define UART_PORT_MAX 4 +#define UART_FIFO_SIZE 16 + +#define UART_PORT_BASE(b,i) ((b) + 0x4000 * (i)) + +/* + * controller registers + */ +#define REG32_PTR_T volatile uint32_t * + +#define ULCON(ba) (*((REG32_PTR_T)((ba) + 0x00))) /* line control */ +#define UCON(ba) (*((REG32_PTR_T)((ba) + 0x04))) /* control */ +#define UFCON(ba) (*((REG32_PTR_T)((ba) + 0x08))) /* FIFO control */ +#define UMCON(ba) (*((REG32_PTR_T)((ba) + 0x0C))) /* modem control */ +#define UTRSTAT(ba) (*((REG32_PTR_T)((ba) + 0x10))) /* Tx/Rx status */ +#define UERSTAT(ba) (*((REG32_PTR_T)((ba) + 0x14))) /* Rx error status */ +#define UFSTAT(ba) (*((REG32_PTR_T)((ba) + 0x18))) /* FIFO status */ +#define UMSTAT(ba) (*((REG32_PTR_T)((ba) + 0x1C))) /* modem status */ +#define UTXH(ba) (*((REG32_PTR_T)((ba) + 0x20))) /* transmission hold */ +#define URXH(ba) (*((REG32_PTR_T)((ba) + 0x24))) /* receive buffer */ +#define UBRDIV(ba) (*((REG32_PTR_T)((ba) + 0x28))) /* baud rate divisor */ +#define UABRCNT(ba) (*((REG32_PTR_T)((ba) + 0x2c))) /* autobaud counter */ +#define UABRSTAT(ba) (*((REG32_PTR_T)((ba) + 0x30))) /* autobaud status */ +#define UBRCONTX(ba) (*((REG32_PTR_T)((ba) + 0x34))) /* Tx frame config */ +#define UBRCONRX(ba) (*((REG32_PTR_T)((ba) + 0x38))) /* Rx frame config */ + +/* ULCON register */ +#define ULCON_DATA_BITS_MASK 0x3 +#define ULCON_DATA_BITS_POS 0 +#define ULCON_DATA_BITS_5 0 +#define ULCON_DATA_BITS_6 1 +#define ULCON_DATA_BITS_7 2 +#define ULCON_DATA_BITS_8 3 + +#define ULCON_STOP_BITS_MASK 0x1 +#define ULCON_STOP_BITS_POS 2 +#define ULCON_STOP_BITS_1 0 +#define ULCON_STOP_BITS_2 1 + +#define ULCON_PARITY_MASK 0x7 +#define ULCON_PARITY_POS 3 +#define ULCON_PARITY_NONE 0 +#define ULCON_PARITY_ODD 4 +#define ULCON_PARITY_EVEN 5 +#define ULCON_PARITY_FORCE_1 6 +#define ULCON_PARITY_FORCE_0 7 + +#define ULCON_INFRARED_EN_BIT (1 << 6) + +/* UCON register */ +#define UCON_RX_MODE_MASK 0x3 +#define UCON_RX_MODE_POS 0 + +#define UCON_TX_MODE_MASK 0x3 +#define UCON_TX_MODE_POS 2 + +#define UCON_MODE_DISABLED 0 +#define UCON_MODE_INTREQ 1 /* INT request or polling mode */ +#define UCON_MODE_UNDEFINED 2 /* Not defined, DMAREQ signal 1 ??? */ +#define UCON_MODE_DMAREQ 3 /* DMA request (signal 0) */ + +#define UCON_SEND_BREAK_BIT (1 << 4) +#define UCON_LOOPBACK_BIT (1 << 5) +#define UCON_RX_TOUT_EN_BIT (1 << 7) /* Rx timeout enable */ + +#define UCON_CLKSEL_MASK 0x1 +#define UCON_CLKSEL_POS 10 +#define UCON_CLKSEL_PCLK 0 /* internal */ +#define UCON_CLKSEL_ECLK 1 /* external */ + +#define UCON_RX_TOUT_INT_BIT (1 << 11) /* Rx timeout INT enable */ +#define UCON_RX_INT_BIT (1 << 12) /* Rx INT enable */ +#define UCON_TX_INT_BIT (1 << 13) /* Tx INT enable */ +#define UCON_ERR_INT_BIT (1 << 14) /* Rx error INT enable */ +#define UCON_MODEM_INT_BIT (1 << 15) /* modem INT enable (TBC) */ +#define UCON_AUTOBR_INT_BIT (1 << 16) /* autobauding INT enable */ +#define UCON_AUTOBR_START_BIT (1 << 17) /* autobauding start/stop */ + +/* UFCON register */ +#define UFCON_FIFO_ENABLE_BIT (1 << 0) +#define UFCON_RX_FIFO_RST_BIT (1 << 1) +#define UFCON_TX_FIFO_RST_BIT (1 << 2) + +#define UFCON_RX_FIFO_TRG_MASK 0x3 +#define UFCON_RX_FIFO_TRG_POS 4 +#define UFCON_RX_FIFO_TRG_4 0 +#define UFCON_RX_FIFO_TRG_8 1 +#define UFCON_RX_FIFO_TRG_12 2 +#define UFCON_RX_FIFO_TRG_16 3 + +#define UFCON_TX_FIFO_TRG_MASK 0x3 +#define UFCON_TX_FIFO_TRG_POS 6 +#define UFCON_TX_FIFO_TRG_EMPTY 0 +#define UFCON_TX_FIFO_TRG_4 1 +#define UFCON_TX_FIFO_TRG_8 2 +#define UFCON_TX_FIFO_TRG_12 3 + +/* UMCON register */ +#define UMCON_RTS_BIT (1 << 0) +#define UMCON_AUTO_FLOW_CTRL_BIT (1 << 4) + +/* UTRSTAT register */ +#define UTRSTAT_RXBUF_RDY_BIT (1 << 0) +#define UTRSTAT_TXBUF_EMPTY_BIT (1 << 1) +#define UTRSTAT_TX_EMPTY_BIT (1 << 2) +#define UTRSTAT_RX_TOUT_INT_BIT (1 << 3) /* Rx timeout INT status */ +#define UTRSTAT_RX_INT_BIT (1 << 4) +#define UTRSTAT_TX_INT_BIT (1 << 5) +#define UTRSTAT_ERR_INT_BIT (1 << 6) +#define UTRSTAT_MODEM_INT_BIT (1 << 7) /* modem INT status (TBC) */ +#define UTRSTAT_AUTOBR_INT_BIT (1 << 8) /* autobauding INT status */ + +/* UERSTAT register */ +#define UERSTAT_OVERRUN_BIT (1 << 0) +#define UERSTAT_PARITY_ERR_BIT (1 << 1) +#define UERSTAT_FRAME_ERR_BIT (1 << 2) +#define UERSTAT_BREAK_DETECT_BIT (1 << 3) + +/* UFSTAT register */ +#define UFSTAT_RX_FIFO_CNT_MASK 0xf +#define UFSTAT_RX_FIFO_CNT_POS 0 + +#define UFSTAT_TX_FIFO_CNT_MASK 0xf +#define UFSTAT_TX_FIFO_CNT_POS 4 + +#define UFSTAT_RX_FIFO_FULL_BIT (1 << 8) +#define UFSTAT_TX_FIFO_FULL_BIT (1 << 9) +#define UFSTAT_RX_FIFO_ERR_BIT (1 << 10) /* clears when reading UERSTAT + for the last pending error */ +/* UMSTAT register */ +#define UMSTAT_CTS_ACTIVE_BIT (1 << 0) +#define UMSTAT_CTS_DELTA_BIT (1 << 4) + +/* Bitrate: + * + * Master UCLK clock is divided by 16 to serialize data, UBRDIV is + * used to configure nominal bit width, NBW = (UBRDIV+1)*16 in UCLK + * clock ticks. + * + * Fine tuning works shrining/expanding each individual bit of each + * frame. Each bit width can be incremented/decremented by 1/16 of + * nominal bit width, it seems UCLK is divided by 17 for expanded + * bits and divided by 15 for compressed bits. A whole frame of N + * bits can be shrined or expanded up to (NBW * N / 16) UCLK clock + * ticks (in 1/16 steps). + */ +/* UBRCONx register */ +#define UC_FRAME_MAX_LEN 12 /* 1 start + 8 data + 1 par + 2 stop */ +#define UBRCON_JITTER_MASK 0x3 +#define UBRCON_JITTER_POS(bit) ((bit) << 1) /* 0..UC_FRAME_MAX_LEN-1 */ + +#define UBRCON_JITTER_NONE 0 /* no jitter for this bit */ +#define UBRCON_JITTER_INC 1 /* increment 1/16 bit width */ +#define UBRCON_JITTER_UNUSED 2 /* does nothing */ +#define UBRCON_JITTER_DEC 3 /* decremet 1/16 bit width */ + +/* Autobauding: + * + * Initial UABRSTAT is NOT_INIT, it goes to READY when either of + * UCON_AUTOBR bits are enabled for the first time. + * + * Interrupts are enabled/disabled using UCON_AUTOBR_INT_BIT and + * checked using UTRSTAT_AUTOBR_INT_BIT, writing this bit cleans the + * interrupt. + * + * When UCON_AUTOBR_START_BIT is enabled, autobauding starts and the + * hardware waits for a low pulse on RX line. + * + * Once autobauding is started, when a falling edge is detected on + * the RX line, UABRSTAT changes to COUNTING status, an internal + * counter starts incrementing at UCLK clock frequency. During + * COUNTING state, UABRCNT reads as the value of the previous ABR + * count, not the value of the current internal count. + * + * Count finish when a rising edge is detected on the line, at this + * moment internal counter stops and it can be read using UABRCNT + * register, UABRSTAT goes to READY, AUTOBR_START_BIT is disabled, + * and an interrupt is raised if UCON_AUTOBR_INT_BIT is enabled. + */ +/* UABRSTAT register */ +#define UABRSTAT_STATUS_MASK 0x3 +#define UABRSTAT_STATUS_POS 0 + +#define UABRSTAT_STATUS_NOT_INIT 0 /* initial status */ +#define UABRSTAT_STATUS_READY 1 /* machine is ready */ +#define UABRSTAT_STATUS_COUNTING 2 /* count in progress */ + + +/* + * structs + */ +struct uartc +{ + /* static configuration */ + const uint32_t baddr; + /* private */ + struct uartc_port *port_l[UART_PORT_MAX]; +}; + +struct uartc_port +{ + /* static configuration */ + struct uartc * const uartc; + const uint8_t id; /* port number */ + const uint8_t rx_trg; /* UFCON_RX_FIFO_TRG_xxx */ + const uint8_t tx_trg; /* UFCON_TX_FIFO_TRG_xxx */ + const uint8_t clksel; /* UFCON_CLKSEL_xxx */ + const uint32_t clkhz; /* UCLK (PCLK or ECLK) frequency */ + void (* const tx_cb) (int len); /* ISRs */ + void (* const rx_cb) (int len, char *data, char *err, uint32_t abr_cnt); + + /* private */ + uint32_t baddr; + uint32_t utrstat_int_mask; + bool abr_aborted; + uint8_t rx_data[UART_FIFO_SIZE]; /* data buffer for rx_cb */ + uint8_t rx_err[UART_FIFO_SIZE]; /* error buffer for rx_cb */ + +#ifdef UC8702_DEBUG + uint32_t n_tx_bytes; + uint32_t n_rx_bytes; + uint32_t n_ovr_err; + uint32_t n_parity_err; + uint32_t n_frame_err; + uint32_t n_break_detect; + uint32_t n_abnormal0; + uint32_t n_abnormal1; +#endif +}; + + +/* + * uc8702 low level API + */ + +/* Initialization */ +void uartc_open(struct uartc* uartc); +void uartc_close(struct uartc* uartc); +void uartc_port_open(struct uartc_port *port); +void uartc_port_close(struct uartc_port *port); +void uartc_port_rx_onoff(struct uartc_port *port, bool onoff); +void uartc_port_tx_onoff(struct uartc_port *port, bool onoff); + +/* Configuration */ +void uartc_port_config(struct uartc_port *port, unsigned int speed, + uint8_t data_bits, uint8_t parity, uint8_t stop_bits); +void uartc_port_set_bitrate(struct uartc_port *port, unsigned int speed); +void uartc_port_set_rx_mode(struct uartc_port *port, uint32_t mode); +void uartc_port_set_tx_mode(struct uartc_port *port, uint32_t mode); + +/* Transmit */ +bool uartc_port_tx_ready(struct uartc_port *port); +void uartc_port_tx_byte(struct uartc_port *port, uint8_t ch); +void uartc_port_send_byte(struct uartc_port *port, uint8_t ch); + +/* Receive */ +bool uartc_port_rx_ready(struct uartc_port *port); +uint8_t uartc_port_rx_byte(struct uartc_port *port); +uint8_t uartc_port_read_byte(struct uartc_port *port); + +/* Autobauding */ +void uartc_port_abr_start(struct uartc_port *port); +void uartc_port_abr_stop(struct uartc_port *port); + +/* ISR */ +void uartc_callback(struct uartc *uartc, int dev); + +#ifdef UC8702_DEBUG +enum { + ABR_INFO_ST_IDLE, + ABR_INFO_ST_LAUNCHED, + ABR_INFO_ST_COUNTING, + ABR_INFO_ST_ABNORMAL +}; + +void uartc_port_get_line_info(struct uartc_port *port, + int *tx_status, int *rx_status, + int *tx_speed, int *rx_speed, char *line_cfg); + +int uartc_port_get_abr_info(struct uartc_port *port, unsigned int *abr_cnt); +#endif +#endif /* __UC8702_H__ */ -- cgit v1.2.3