From 57969698ced265492d2007d39e350b337e163ea4 Mon Sep 17 00:00:00 2001
From: Cástor Muñoz <cmvidal@gmail.com>
Date: Mon, 10 Nov 2014 02:39:16 +0100
Subject: iPod Classic: update timer API using 32-bit timers.

Change-Id: I49dab8ae955a339ad0a27402fa21caa411c4ecf6
Reviewed-on: http://gerrit.rockbox.org/1032
Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
---
 firmware/target/arm/s5l8702/timer-s5l8702.c | 57 +++++++++++------------------
 1 file changed, 22 insertions(+), 35 deletions(-)

(limited to 'firmware/target/arm/s5l8702/timer-s5l8702.c')

diff --git a/firmware/target/arm/s5l8702/timer-s5l8702.c b/firmware/target/arm/s5l8702/timer-s5l8702.c
index 61d4d590e4..7c69ab123a 100644
--- a/firmware/target/arm/s5l8702/timer-s5l8702.c
+++ b/firmware/target/arm/s5l8702/timer-s5l8702.c
@@ -26,13 +26,11 @@
 #include "system.h"
 #include "timer.h"
 
-//TODO: This needs calibration once we figure out the clocking
-
-void INT_TIMERC(void)
+void INT_TIMERF(void)
 {
     /* clear interrupt */
-    TCCON = TCCON;
-    
+    TSTAT = (0x07 << 16);
+
     if (pfn_timer != NULL) {
         pfn_timer();
     }
@@ -40,12 +38,8 @@ void INT_TIMERC(void)
 
 bool timer_set(long cycles, bool start)
 {
-    static const int cs_table[] = {1, 2, 4, 6};
-    int prescale, cs;
-    long count;
-
-    /* stop and clear timer */
-    TCCMD = (1 << 1);   /* TD_CLR */
+    /* stop timer */
+    TFCMD = (0 << 0);       /* TF_ENABLE */
 
     /* optionally unregister any previously registered timer user */
     if (start) {
@@ -55,40 +49,33 @@ bool timer_set(long cycles, bool start)
         }
     }
 
-    /* scale the count down with the clock select */
-    for (cs = 0; cs < 4; cs++) {
-        count = cycles >> cs_table[cs];
-        if ((count < 65536) || (cs == 3)) {
-            break;
-        }
-    }
-    
-    /* scale the count down with the prescaler */
-    prescale = 1;
-    while (count >= 65536) {
-        count >>= 1;
-        prescale <<= 1;
-    }
+    /* There is an odd behaviour when the 32-bit timers are launched
+       for the first time, the interrupt status bits are set and an
+       unexpected interrupt is generated if they are enabled. A way to
+       workaround this is to write the data registers before clearing
+       the counter. */
+    TFDATA0 = cycles;
+    TFCMD = (1 << 1);       /* TF_CLR */
 
     /* configure timer */
-    TCCON = (1 << 12) |     /* TD_INT0_EN */
-            (cs << 8) |     /* TS_CS */
-            (0 << 4);       /* TD_MODE_SEL, 0 = interval mode */
-    TCPRE = prescale - 1;
-    TCDATA0 = count;
-    TCCMD = (1 << 0);       /* TD_ENABLE */
-    
+    TFCON = (1 << 12) |     /* TF_INT0_EN */
+            (4 << 8) |      /* TF_CS, 4 = ECLK / 1 */
+            (1 << 6) |      /* use ECLK (12MHz) */
+            (0 << 4);       /* TF_MODE_SEL, 0 = interval mode */
+    TFPRE = 0;              /* no prescaler */
+
+    TFCMD = (1 << 0);       /* TF_ENABLE */
+
     return true;
 }
 
 bool timer_start(void)
 {
-    TCCMD = (1 << 0);       /* TD_ENABLE */
+    TFCMD = (1 << 0);       /* TF_ENABLE */
     return true;
 }
 
 void timer_stop(void)
 {
-    TCCMD = (0 << 0);       /* TD_ENABLE */
+    TFCMD = (0 << 0);       /* TF_ENABLE */
 }
-
-- 
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