From 7b10ef9a7c55764d1b6815fd0871cb51ff0205f9 Mon Sep 17 00:00:00 2001 From: Marcoen Hirschberg Date: Fri, 27 Jun 2008 23:24:34 +0000 Subject: initial Meizu M6SL port (take 2) git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17819 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/arm/s5l8700/system-s5l8700.c | 168 +++++++++++++++++++++++++++ 1 file changed, 168 insertions(+) create mode 100644 firmware/target/arm/s5l8700/system-s5l8700.c (limited to 'firmware/target/arm/s5l8700/system-s5l8700.c') diff --git a/firmware/target/arm/s5l8700/system-s5l8700.c b/firmware/target/arm/s5l8700/system-s5l8700.c new file mode 100644 index 0000000000..2d87cc8c9a --- /dev/null +++ b/firmware/target/arm/s5l8700/system-s5l8700.c @@ -0,0 +1,168 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2007 by Rob Purchase + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +#include "kernel.h" +#include "system.h" +#include "panic.h" + +#define default_interrupt(name) \ + extern __attribute__((weak,alias("UIRQ"))) void name (void) + +void irq_handler(void) __attribute__((interrupt ("IRQ"), naked)); +void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked)); + +default_interrupt(EXT0); +default_interrupt(EXT1); +default_interrupt(EXT2); +default_interrupt(EINT_VBUS); +default_interrupt(EINTG); +default_interrupt(INT_TIMERA); +default_interrupt(INT_WDT); +default_interrupt(INT_TIMERB); +default_interrupt(INT_TIMERC); +default_interrupt(INT_TIMERD); +default_interrupt(INT_DMA); +default_interrupt(INT_ALARM_RTC); +default_interrupt(INT_PRI_RTC); +default_interrupt(RESERVED1); +default_interrupt(INT_UART); +default_interrupt(INT_USB_HOST); +default_interrupt(INT_USB_FUNC); +default_interrupt(INT_LCDC_0); +default_interrupt(INT_LCDC_1); +default_interrupt(INT_ECC); +default_interrupt(INT_CALM); +default_interrupt(INT_ATA); +default_interrupt(INT_UART0); +default_interrupt(INT_SPDIF_OUT); +default_interrupt(INT_SDCI); +default_interrupt(INT_LCD); +default_interrupt(INT_SPI); +default_interrupt(INT_IIC); +default_interrupt(RESERVED2); +default_interrupt(INT_MSTICK); +default_interrupt(INT_ADC_WAKEUP); +default_interrupt(INT_ADC); + + + +static void (* const irqvector[])(void) = +{ + EXT0,EXT1,EXT2,EINT_VBUS,EINTG,INT_TIMERA,INT_WDT,INT_TIMERB, + INT_TIMERC,INT_TIMERD,INT_DMA,INT_ALARM_RTC,INT_PRI_RTC,RESERVED1,INT_UART,INT_USB_HOST, + INT_USB_FUNC,INT_LCDC_0,INT_LCDC_1,INT_ECC,INT_CALM,INT_ATA,INT_UART0,INT_SPDIF_OUT, + INT_SDCI,INT_LCD,INT_SPI,INT_IIC,RESERVED2,INT_MSTICK,INT_ADC_WAKEUP,INT_ADC +}; + +static const char * const irqname[] = +{ + "EXT0","EXT1","EXT2","EINT_VBUS","EINTG","INT_TIMERA","INT_WDT","INT_TIMERB", + "INT_TIMERC","INT_TIMERD","INT_DMA","INT_ALARM_RTC","INT_PRI_RTC","Reserved","INT_UART","INT_USB_HOST", + "INT_USB_FUNC","INT_LCDC_0","INT_LCDC_1","INT_ECC","INT_CALM","INT_ATA","INT_UART0","INT_SPDIF_OUT", + "INT_SDCI","INT_LCD","INT_SPI","INT_IIC","Reserved","INT_MSTICK","INT_ADC_WAKEUP","INT_ADC" +}; + +static void UIRQ(void) +{ + unsigned int offset = INTOFFSET; + panicf("Unhandled IRQ %02X: %s", offset, irqname[offset]); +} + +void irq_handler(void) +{ + /* + * Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c + */ + + asm volatile( "stmfd sp!, {r0-r7, ip, lr} \n" /* Store context */ + "sub sp, sp, #8 \n"); /* Reserve stack */ + + int irq_no = INTOFFSET; /* Read clears the corresponding IRQ status */ + + if ((irq_no & (1<<31)) == 0) /* Ensure invalid flag is not set */ + { + irqvector[irq_no](); + } + + asm volatile( "add sp, sp, #8 \n" /* Cleanup stack */ + "ldmfd sp!, {r0-r7, ip, lr} \n" /* Restore context */ + "subs pc, lr, #4 \n"); /* Return from IRQ */ +} + +void fiq_handler(void) +{ + asm volatile ( + "subs pc, lr, #4 \r\n" + ); +} + + +static void gpio_init(void) +{ +} + +static void clock_init(void) +{ +} + + +void system_init(void) +{ +} + +void system_reboot(void) +{ +} + +int system_memory_guard(int newmode) +{ + (void)newmode; + return 0; +} + +#ifdef HAVE_ADJUSTABLE_CPU_FREQ + +void set_cpu_frequency(long frequency) +{ + if (cpu_frequency == frequency) + return; + + /* CPU/COP frequencies can be scaled between Fbus (min) and Fsys (max). + Fbus should not be set below ~32Mhz with LCD enabled or the display + will be garbled. */ + if (frequency == CPUFREQ_MAX) + { + } + else if (frequency == CPUFREQ_NORMAL) + { + } + else + { + } + + asm volatile ( + "nop \n\t" + "nop \n\t" + "nop \n\t" + ); + + cpu_frequency = frequency; +} + +#endif -- cgit v1.2.3