From e5c815272dc8436f487c3b6ed238d80910f0fde0 Mon Sep 17 00:00:00 2001
From: Michael Sparmann <theseven@rockbox.org>
Date: Wed, 17 Feb 2010 15:57:53 +0000
Subject: Add more information to the battery debug screen for Nano2G

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24723 a1c6a512-1295-4272-9138-f99709370657
---
 firmware/target/arm/s5l8700/crt0.S | 96 +++++++++++++++++++-------------------
 1 file changed, 48 insertions(+), 48 deletions(-)

(limited to 'firmware/target/arm/s5l8700/crt0.S')

diff --git a/firmware/target/arm/s5l8700/crt0.S b/firmware/target/arm/s5l8700/crt0.S
index bb6d910e22..fe2a2c1980 100644
--- a/firmware/target/arm/s5l8700/crt0.S
+++ b/firmware/target/arm/s5l8700/crt0.S
@@ -260,64 +260,64 @@ start_loc:
 
 #if defined(MEIZU_M6SP) || defined(MEIZU_M3)
     /* setup SDRAM for Meizu M6SP */
-    ldr r1, =0x38200000
-    // configure SDR drive strength and pad settings
+    ldr r1, =0x38200000
+    // configure SDR drive strength and pad settings
     mov r0, #SDR_DSS_SEL_B
-    str r0, [r1, #0x4C] // MIU_DSS_SEL_B
+    str r0, [r1, #0x4C] // MIU_DSS_SEL_B
     mov r0, #SDR_DSS_SEL_O
-    str r0, [r1, #0x50] // MIU_DSS_SEL_O
+    str r0, [r1, #0x50] // MIU_DSS_SEL_O
     mov r0, #SDR_DSS_SEL_C
-    str r0, [r1, #0x54] // MIU_DSS_SEL_C
-    mov r0, #2
-    str r0, [r1, #0x60] // SSTL2_PAD_ON
-    // select SDR mode
+    str r0, [r1, #0x54] // MIU_DSS_SEL_C
+    mov r0, #2
+    str r0, [r1, #0x60] // SSTL2_PAD_ON
+    // select SDR mode
     ldr r0, [r1, #0x40]
-    mov r2, #0xFFFDFFFF
-    and r0, r0, r2
-    orr r0, r0, #1
-    str r0, [r1, #0x40] // MIUORG
+    mov r2, #0xFFFDFFFF
+    and r0, r0, r2
+    orr r0, r0, #1
+    str r0, [r1, #0x40] // MIUORG
     // set controller configuration
     mov r0, #SDR_CONFIG
     str r0, [r1]        // MIUCON
-    // set SDRAM timing
+    // set SDRAM timing
     ldr r0, =SDR_TIMING
-    str r0, [r1, #0x10] // MIUSDPARA
-    // set refresh rate
-    mov r0, #0x1080
-    str r0, [r1, #0x08] // MIUAREF
-    // initialise SDRAM 
-    mov r0, #0x003
-    str r0, [r1, #0x04] // MIUCOM = nop
-    ldr r0, =0x203
-    str r0, [r1, #0x04] // MIUCOM = precharge all banks
-    nop
-    nop
-    nop
-    ldr r0, =0x303
-    str r0, [r1, #0x04] // MIUCOM = auto-refresh
-    nop
-    nop
-    nop
-    nop
-    str r0, [r1, #0x04] // MIUCOM = auto-refresh
-    nop
-    nop
-    nop
-    nop
-    str r0, [r1, #0x04] // MIUCOM = auto-refresh
-    nop
-    nop
-    nop
-    nop
-    // set mode register
+    str r0, [r1, #0x10] // MIUSDPARA
+    // set refresh rate
+    mov r0, #0x1080
+    str r0, [r1, #0x08] // MIUAREF
+    // initialise SDRAM 
+    mov r0, #0x003
+    str r0, [r1, #0x04] // MIUCOM = nop
+    ldr r0, =0x203
+    str r0, [r1, #0x04] // MIUCOM = precharge all banks
+    nop
+    nop
+    nop
+    ldr r0, =0x303
+    str r0, [r1, #0x04] // MIUCOM = auto-refresh
+    nop
+    nop
+    nop
+    nop
+    str r0, [r1, #0x04] // MIUCOM = auto-refresh
+    nop
+    nop
+    nop
+    nop
+    str r0, [r1, #0x04] // MIUCOM = auto-refresh
+    nop
+    nop
+    nop
+    nop
+    // set mode register
     mov r0, #SDR_MRS
-    str r0, [r1, #0x0C] // MIUMRS
-    ldr r0, =0x103
-    str r0, [r1, #0x04] // MIUCOM = mode register set
+    str r0, [r1, #0x0C] // MIUMRS
+    ldr r0, =0x103
+    str r0, [r1, #0x04] // MIUCOM = mode register set
     ldr r0, =SDR_EMRS
-    str r0, [r1, #0x0C] // MIUMRS
-    ldr r0, =0x103
-    str r0, [r1, #0x04] // MIUCOM = mode register set
+    str r0, [r1, #0x0C] // MIUMRS
+    ldr r0, =0x103
+    str r0, [r1, #0x04] // MIUCOM = mode register set
 #endif /* MEIZU_M6SP */
 
     mov r1, #0x1
-- 
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